Radix-2 Single-path Delay Feedback Research Articles

A Flexible-Channel MDF Architecture for Pipelined Radix-2 FFT

This paper proposes a flexible-channel multiple-path delay feedback (FC-MDF) pipelined fast Fourier transform architecture, which is based on Radix-2 FFT algorithm. The FC-MDF can be dynamically configured to accommodate two levels of FFT size. Different from the bypass structure that prevents the sequence data from passing through the preceding stages when the FFT size is reduced, the FC-MDF can be dynamically configured into single-channel mode when calculating larger size sequences, and into dual-channel mode when calculating smaller size sequences by taking advantage of the first stage 0and sharing of processing elements in subsequent stages. The proposed architecture increases the utilization of computing units, including butterfly and complex multiplier, from 50% to 100%, and provides twice the throughput in dual-channel mode, compared with the traditional Radix-2 single-path delay feedback (R2SDF) architecture. We implemented this structure on Xilinx FPGAs. The experimental results show that, compared with current SDF, the proposed FC-MDF significantly optimizes the proportion of resources when the FFT size is reduced.

High-Speed Continuous Wavelet Transform Processor for Vital Signal Measurement Using Frequency-Modulated Continuous Wave Radar

This paper proposes a high-speed continuous wavelet transform (CWT) processor to analyze vital signals extracted from a frequency-modulated continuous wave (FMCW) radar sensor. The proposed CWT processor consists of a fast Fourier transform (FFT) module, complex multiplier module, and inverse FFT (IFFT) module. For high-throughput processing, the FFT and IFFT modules are designed with the pipeline FFT architecture of radix-2 single-path delay feedback (R2SDF) and mixed-radix multipath delay commutator (MRMDC) architecture, respectively. In addition, the IFFT module and the complex multiplier module perform a four-channel operation to reduce the processing time from repeated operations. Simultaneously, the MRMDC IFFT module minimizes the circuit area by reducing the number of non-trivial multipliers by using a mixed-radix algorithm. In addition, the proposed CWT processor can support variable lengths of 8, 16, 32, 64, 128, 256, 512, and 1024 to analyze various vital signals. The proposed CWT processor was implemented in a field-programmable gate array (FPGA) device and verified through the measurement of heartbeat and respiration from an FMCW radar sensor. Experimental results showed that the proposed CWT processor can reduce the processing time by 48.4-fold and 40.7-fold compared to MATLAB software with Intel i7 CPU. Moreover, it can be confirmed that the proposed CWT processor can reduce the processing time by 73.3% compared to previous FPGA-based implementations.

Design and implementation of pipelined SDF FFT architecture for sustainable industrial noise suppression in Digital Hearing Aids

This article implements Industrial Noise Reduction for Digital Hearing Aids, and the proposed solution uses the R22SDF FFT architecture to perform discrete time to frequency conversion. Acoustic feedbacks cause the Hearing Aid to develop a high-pitched tone. The 64-point Pipelined Radix 22 Single Path Delay Feedback (R22SDF) FFT Processor reduces these disturbances. In FFT, O (Nlog2N) and O (N/2log2N) minimize the product count and summation order, respectively. This paper presents a new solution based on a 64-point Pipelined R22SDF FFT architecture to reduce processing delay in existing Digital Hearing Aid processors. MATLAB Simulink and HDL Software were used to generate the simulated output. In the experimentation the hearing Aid input noises from different industrial environment is fed to proposed SDF FFT and filtered using octave filter to achieve high quality speech with SNR greater than 20 db. Using the proposed SDF FFT architecture, speech quality from hearing aid under different noise environment and signal under different environment shows 85% more clarity when compared to existing architectures.

Precision Adaptive MFCC Based on R2SDF-FFT and Approximate Computing for Low-Power Speech Keywords Recognition

This paper presents system-architecture-circuits co-designs for computing the MFCC feature extraction for speech keywords recognition. The trade-off between accuracy and power consumption under various background noises is achieved by using the 8-stage radix-2 single-path delay feedback FFT (R2SDF-FFT) and the precision self-adaptive architecture with approximate computing. The R2SDF-FFT structure with the fine-grained bit-width quantization can reduce 35.7% of memory size. Approximate multiplication and addition with Dual-Vdd are proposed to further improve the FFT computing energy efficiency. Finally, we present the precision self-adaptive MFCC architecture with the proposed FFT, which can be dynamically configured to use two calculation modes with different hardware settings according to the input speech background noise. Implemented and evaluated under 22 nm technology, the power consumption of the proposed design can be reduced by up to 76.3%, while the accuracy increased by 0.8%.

Area-Efficient Short-Time Fourier Transform Processor for Time–Frequency Analysis of Non-Stationary Signals

In this paper, we propose an area-efficient short-time Fourier transform (STFT) processor that can perform time–frequency analysis of non-stationary signals in real time, which is essential for voice or radar-signal processing systems. STFT processors consist of a windowing module and a fast Fourier transform processor. The length of the window function is related to the time–frequency resolution, and the required window length varies depending on the application. In addition, the window function needs to overlap the input data samples to minimize the data loss in the window boundary, and overlap ratios of 25%, 50%, and 75% are generally used. Therefore, the STFT processor should ideally support a variable window length and overlap ratio and be implemented with an efficient hardware architecture for real-time time–frequency analysis. The proposed STFT processor is based on the radix-4 multi-path delay commutator (R4MDC) pipeline architecture and supports a variable length of 16, 64, 256, and 1024 and overlap ratios of 25%, 50%, and 75%. Moreover, the proposed STFT processor can be implemented with very low complexity by having a relatively lower number of delay elements, which are the ones that increase complexity in the most STFT processors. The proposed STFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using a standard cell library in a 65 nm CMOS process. The proposed STFT processor results in logic gates of 197,970, which is 63% less than that of the conventional radix-2 single-path delay feedback (R2SDF) based STFT processor.

Hardware-Efficient Bartlett Spectral Density Estimator Based on Optimized R22FFT Processor Using CCSSI Method

This paper offers a novel, low-power, hardware-efficient, yet high-frequency architecture for a power spectral density (PSD) estimator, based on the Bartlett method, for low-power biomedical applications. The Bartlett method is a nonparametric method for PSD estimation. The proposed architecture operates based on a modified multiplierless 64-point optimized radix-22single-path delay feedback (R22SDF) FFT processor. To obtain the final result, it also uses modified safe-scaling in a way that removes the need to use several extra hardware units. It takes advantage of combined coefficient selection and shift-and-add implementation (CCSSI) for computing twiddle factors which is a new algorithm based on digital computer coordinate rotation (CORDIC) for generating trigonometric values. The proposed method has the capability of operating on short word lengths (WLs). Artix-7 is the FPGA used in this research and Verilog is the language used for hardware design. For 8-bit WL and 244-mW power, a frequency of 286 MHz has been achieved. Several vital signals are used for performance comparison of the proposed technique with state-of-the-art designs.

Efficient-Scheduling Parallel Multiplier-Based Ring-LWE Cryptoprocessors

This paper presents a novel architecture for ring learning with errors (LWE) cryptoprocessors using an efficient approach in encryption and decryption operations. By scheduling multipliers to work in parallel, the encryption and decryption time are significantly reduced. In addition, polynomial multiplications are conducted using radix-2 and radix-8 multiple delay feedback (MDF) architecture-based number theoretic transform (NTT) multipliers to speed up the multiplication operation. To reduce the hardware complexity of an NTT multiplier, three bit-reverse operations during the NTT and inverse NTT (INTT) processes are removed. Polynomial additions in the ring-LWE encryption phase are also arranged to work simultaneously to reduce the latency. As a result, the proposed efficient-scheduling parallel multiplier-based ring-LWE cryptoprocessors can achieve higher throughput and efficiency compared with existing architectures. The proposed ring-LWE cryptoprocessors are synthesized and verified using Xilinx VIVADO on a Virtex-7 field programmable gate array (FPGA) board. With security parameters n = 512 and q = 12,289, the proposed cryptoprocessors using radix-2 single-path delay feedback (SDF), radix-2 MDF, and radix-8 MDF multipliers perform encryption in 4.58 μ s, 1.97 μ s, and 0.89 μ s, and decryption in 4.35 μ s, 1.82 μ s, and 0.71 μ s, respectively. A comparison of the obtained throughput and efficiency with those of previous studies proves that the proposed cryptoprocessors achieve a better performance.

Design and Implementation of High-Speed Variable Point Pipelined FFT Processor for OFDM System using Verilog

Objectives: For Orthogonal Frequency Division Multiplexing (OFDM), Fast Fourier Transform (FFT) processoris required. So, in this work, a variable point Pipelined FFT processor is designed by utilizing Verilog language. Further transmitter and receiver blocks are designed to form OFDM system. Methods: Speed enhancement is the key area which is been looked into this project work. Pipelined Architecture that is going to be implemented is RS2DF (Radix-2 Single path Delay Feedback). Standard FPGA Flow is adapted to implement this project i.e., right from specification to bit file generation. Simulations and Synthesis will be done using Questasim and Xilinx ISE. Verilog Simulations will be compared with in-built MATLAB FFT Core. MATLAB is used for reference and verification. Findings: This Project clarified the usage of FFT IP and OFDM in Xilinx ISE focusing on a specific family of FPGA. The execution of the proposed algorithm ought to perform superior to anything the base algorithm with the all-out basic way getting additionally advanced along these lines expanding the speed of activity. maximum operation frequency achieved was 236.189MHz but in base paper maximum operation frequency was 30Mhz. The systems utilized are Interna1 and externa1 Pipe1ining of modules and Distributed LUT based idea, the target of the above methods is to lessen the basic way deferral and increment the general speed of activity of structure, the disadvantage is the increments in area and output latency. Area is not of a much issue as present day days FPGAs has immense measure of assets. Output 1atency should be taken consideration with additional rationale at whatever point FFT is coordinated with other system modules. Application: The project depicts technique for streamlining timing basic ways of FFT to work at higher-speeds, to be utilized as a feature of LTE Protoca1 or any wire1ess protoco1 such as WLAN and LDACS. Keywords: Fast Fourier Transform (FFT), Hardware Description Language (HDL), Orthogonal Frequency Division Multiplexing (OFDM), Pipeline, Verilog

EFFICIENT ARCHITECTURE OF COMBINED RADIX DIF ALGORITHM FOR MIMO-OFDM APPLICATION

An efficient design of combined radix-2 Single path Delay Feedback (SDF)-Single path Delay Commutator (SDC)-Decimation In Frequency (DIF) algorithm is proposed in this paper which can be used in Orthogonal Frequency Division Multiplexing (OFDM) with Multiple Input Multiple Output (MIMO) applications. The MIMO-OFDM communication system has tremendous and swift growth in various applications used over last decade, especially wireless and digital communication where adaptability, reconfigurability, less chip size, hardware improvements, and lower power consumption are mandatory requirements during communication. The main aim of this structure is to improve the performance of combined Fast Fourier Transform (FFT) for the MIMO-OFDM system and also to reduce the complexity of the hardware.

Design of Combined Radix-2, Radix- 4 and Radix-8 based Single Path Delay Feedback (SDF) FFT

Objectives: FFT algorithm is used for enhancing the performance of DFT.In the previous years, various types of FFT algorithms have been introduced. Particularly, the pipeline algorithms have been reputed as proper algorithms for processing high-speed data. Some pipeline FFT algorithms like split radix, radix-2 and the mixed radix have been developed. Methods: In the existing method of Radix-2 SDF FFT has more hardware utilization and also computational stages are increased. Findings: To conquer this problem, we developed a combined radix-2, 4 & 8 butterfly elements based Single path Delay Feedback (SDF) fast fourier transform method for reducing the computational stages in this paper. The developed method has the identical number of multipliers and the smaller number of stages and butterfly elements than the existing radix-2 FFT. Improvements: This architecture offers 62.47% reduction in LUTs, 58.78% reduction in slices, and 37.85% reduction in delay and 30.86% reduction in power consumption than the existing method.

A Novel VLSI Based Radix-2 Single Path Delay Commutator (R2SDC) FFT Architecture Design

The aim is to design a new architecture called Novel Radix-2 Single path Delay Commutator (R2SDC) for improving the architectural performances of Fast Fourier Transformation (FFT) technique. In proposed new architecture, only commutator structures and complex multipliers are used to convert the time domain signals into frequency domain signals. In order to match the frequency response, delay elements are used appropriately. Traditional pipelined architectures have multiple complex multiplication units for performing frequency transformation techniques. But, proposed R2SDC structure has single complex multiplication unit per stage. Data flow structures of R2SDC architecture has been designed through Very Large Scale Integration (VLSI) System design environment. Proposed novel architecture called R2SDC FFT offers 21.4% improvements in hardware slices, 26.76% improvements in Look Up Tables (LUTs), 23.49% improvements in maximum output required time after clock and 31.88% improvements in power consumptions than traditional pipelined Radix-2 Single path Delay Feedback (R2SDF) FFT architecture. Also proposed architecture offers 4.61% improvements in hardware slices, 6.52% improvements in LUTs and 10.10% improvements in power consumption than combined SDC-SDF FFT architecture. In future, proposed R2DSC FFT architecture will be useful in Orthogonal Frequency Division Multiplexing (OFDM) architecture for estimating the frequency response of digital signals. It will be useful in large distance communications based applications

VLSI Based New Pipelined Architecture Design for Radix-2 FFT

Improvements of wireless digital communication application have large demands on Signal Processing operations. Frequency transformation techniques are recognized as high potential in the field of digital communication. In this study, a new pipelined based Fast Fourier Transformation (FFT) architecture is designed for performing frequency transformation techniques. Delay Feedback (DF) and Delay Commutator (DC) based structures are widely used to perform frequency transformation techniques. A new architecture called “Single path Delay Commutator (SDC)” is introduced in this study to estimate the frequency representation of discrete time input samples. Further, Single path Delay Feedback (SDF) structures are utilized in the final stage of SDC architecture for obtaining response in bit reversing order. Proposed new architecture is named as “Radix-2 Mixed SDC-SDF FFT” To increase the processing speed of FFT architectures, pipelining techniques is introduced in the proposed Mixed SDC-SDF FFT architecture. Hence, the proposed new architecture named as “Pipelined Radix-2 Mixed SDC-SDF FFT”. The performance evaluation of proposed architecture is determined through Very Large Scale Integration (VLSI) System design environment. Less area utilization, low power consumption and high speed are the main concerns in VLSI System design environment. Hence, the aim of proposed new architecture is to reduce the hardware architecture, power consumption and increasing both speed and throughput of the system. Proposed new Pipelined Radix-2 Mixed SDC-SDF FFT architecture offers 17.6% reduction of Slices, 21.65% reduction of LUTs, 45.92% reduction of maximum combinational delay and 24.22% reduction of power consumption than best existing Radix-2 SDF FFT structure.

Area-efficient FFT processor for MIMO-OFDM based SDR systems

In this letter, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed FFT processor can support variable lengths of 64, 128, 256, 512, 1024, 1536 and 2048. By reducing the required number of non-trivial multipliers with a mixed-radix algorithm, the complexity of the proposed FFT processor is dramatically decreased. The proposed FFT processor was designed in a hardware description language (HDL) and synthesized to gate-level circuits using a 0.13µm CMOS standard cell library. With the proposed architecture, the gate count for the proposed FFT processor is 78.8K and the size of memory is 393.22Kbits, which are reduced by 40.9% and 19.7%, respectively, compared with the 4-channel radix-2 single-path delay feedback (R2SDF) with the 4-channel radix-3 SDF (R3SDF) FFT processor. Also, compared with the 4-channel radix-2 multi-path delay commutator (R2MDC) with the 4-channel R3SDF FFT processor, it is shown that the gate count and memory size are reduced by 33.8% and 18.5%, respectively.

Novel FPGA-based pipelined floating point FFT processor

Two novel architectures for pipelined floating point fast Fourier transform on FPGA are presented. The new radix-22 two-path delay feedback (R22TDF) architecture leads to 50% area saving for floating point complex adders compared with the radix-22 single-path delay feedback (R22SDF) architecture. Besides a new hybrid architecture is presented which mixes the R22TDF and R22TDF butterfly structures and is flexible and efficient for FPGA implementation.