Radio Frequency Receiver Front-end Research Articles

An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA With 4.5-dB NF and 11.5-dBm OIP3

In this article, an ultra-low-voltage 2.4-GHz radio frequency (RF) receiver front-end architecture targeting the removal of output flicker noise is presented, making it possible to use zero-IF topology for narrow-band communication standards. The trans-impedance amplifier (TIA) is built on the proposed hybrid operational trans-conductance amplifier (OTA) with a switched-capacitor (SC) amplifier as the first gain stage and an active primary–secondary amplifier as the second gain stage, achieving an imperceptible flicker-noise corner frequency. With the SC gain stage, the interstage common-mode voltage can be set to 0 V, which reduces the minimum supply voltage to 0.5 V. As another benefit, dc offset compensation (DCOC) is performed inherently in the interstage sampling and coupling process. Fabricated in 28-nm RF CMOS process, the front-end prototype, including an on-chip matching inductor, occupies a die area of 0.8 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . Operating in the Industrial Scientific Medical (ISM) frequency band of 2.4 GHz with 1-MHz IF bandwidth, the front end provides a 36–40-dB conversion gain, an 11.5-dBm OIP3, and a flicker-noise corner frequency less than 10 kHz with the supply voltage ranging from 0.5 to 0.6 V. The RF impedance matching network provides passive voltage gain before the low-noise trans-conductance amplifier (LNTA), achieving a 4.5-dB noise figure (NF) with 0.8-mA biasing current in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_m$</tex-math> </inline-formula> stage. With the ultra-low supply voltage and the passive IF gain stage, the power consumption of the proposed front end is only 610 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> W under a 0.53-V supply voltage.

RF Receiver Front-End Employing IIP2-Enhanced 25% Duty-Cycle Quadrature Passive Mixer for Advanced Cellular Applications

This paper proposes a second-order input-referred intercept point (IIP2)-enhanced 25% duty-cycle local oscillator (LO) quadrature passive mixer configuration with developing a wideband radio frequency (RF) receiver front-end, suitable for 4G and 5G new radio (NR) sub-6 GHz applications. By combining mixer switches operated by several combinations of quadrature-phase RF and LO signals, the inherent second-order nonlinear characteristics produced by the asymmetric factors of the mixer are greatly improved without any additional calibration process. This second-order linearity improvement is theoretically analyzed in terms of the 25% duty-cycle mixing operations, and is compared to the linearity characteristic observed in the conventional mixer design. To validate the IIP2 performance improvement, a wideband RF receiver front-end with the proposed mixer design is fabricated in a 65-nm CMOS technology. The implemented receiver front-end incorporates a wideband low noise amplifier with a polyphase filter, the proposed quadrature passive mixers, wideband transimpedance amplifiers, and 25% duty-cycle LO circuitry. The performance is characterized mainly in the long-term evolution and 5G NR frequency bands, which range from 1800 MHz to 2700 MHz. The demonstrated design achieves approximately 16 dB higher mean values of the out-of-band (OB) IIP2s compared to a conventional design approach without calibration. The design also attains conversion gains greater than 43 dB, double-sideband noise figures less than 4.4 dB, OB IIP3s greater than −1.52 dBm, and OB input P1dB greater than −23.1 dBm, for all measured frequency bands even in the presence of transmitter blockers. The proposed configuration, excluding the LO circuitry, consumes a bias current of 17.4 mA with a nominal supply of 1.2 V. The active area of the proposed implemented design is 0.6 mm2.

Linearity improvement in E‐mode ferroelectric GaN MOS‐HEMT using dual gate technology

In this work, an enhancement mode dual gate ferroelectric gallium nitride metal oxide semiconductor-high electron mobility transistor (GaN MOS-HEMT) is proposed with enhanced linearity characteristics. The different DC characteristics of the device are analysed and compared with available experimental data of single gate un-recessed ferroelectric GaN MOS-HEMT. In order to analyse the linearity performance of the devices, a look up table-based large signal model is developed directly from technology computer-aided device simulation results built by feeding different small signal parameters. The different linearity characteristics such as input third-order intercept point (IIP3), the input gain compression point (P1dB), third-order intermodulation (IM3) and the carrier to intermodulation power ratio of both the devices are compared by harmonic balance simulation of the developed large signal models. The interlink between IIP3 and IM3 with transconductance indicates that the broader the transconductance distribution with respect to different gate voltage generates higher IIP3 and lower IM3, which results in an improved linearity performance. The dual gate device shows improved linearity performance resulting in applicability in radiofrequency front end receiver.

Design and Optimization of a Direct-Conversion Double-Balanced Mixer for RF Receiver Front-End

Differential implementation is becoming highly favoured in RFIC (radio frequency integrated circuit) design, notably its high immunity to common-mode noises, acceptable rejection of parasitic coupling, and increased dynamic range. One specific RF front-end building block that is usually designed as a differential circuit is the mixer. This technical paper presents a study of a differential mixer, notably the double-balanced mixer implemented on a direct-conversion architecture in a standard 90nm CMOS (complementary metal-oxide semiconductor) process. Operating frequency is set at 5GHz, which is a typical frequency for RF (radio frequency) receiver. Impedance matching was essential to fully optimize the mixer design. The direct-conversion double-balance mixer design eventually achieved conversion gain of 11.463dB and noise figure of 16.529dB, comparable to mixer designs from past research and studies.

Modeling of an 8–12 GHz receiver front-end based on an in-line MEMS frequency discriminator

This paper focuses on the modeling of an 8–12 GHz RF (radio frequency) receiver front-end based on an in-line MEMS (microelectromechanical systems) frequency discriminator. Actually, the frequency detection is realized by measuring the output dc thermal voltage generated by the MEMS thermoelectric power sensor. Based on this thermal voltage, it has a great potential to tune the resonant frequency of the VCO (voltage controlled oscillator) in the RF receiver front-end application. The equivalent circuit model of the in-line frequency discriminator is established and the measurement verification is also implemented. Measurement and simulation results show that the output dc thermal voltage has a nearly linear relation with frequency. A new construction of RF receiver front-end is then obtained by connecting the in-line frequency discriminator with the voltage controlling port of VCO. Lastly, a systemic simulation is processed by computer-aided software and the real-time simulation waveform at each key point is observed clearly.

RF Front End Receiver for GPS/Galileo L1/E1

Abstract The upcoming Galileo system opens a wide range of new opportunities in the Global Navigation Satellite System (GNSS) market. However, the characteristics of the future signals require the development of new GNSS receivers. This paper presents the devel- oped GNSS receiver architecture (including the Radio Frequency (RF) Front-End and the baseband Hardware (HW) platform), and describes the development of the experimental Global Positioning System (GPS)/Galileo L1/E1 RF Front-End (based on Maxim's MAX2769 chip), capable of being integrated in a space mission, done in the scope of the REAGE project. The results obtained with this new device are presented, focusing on the impact of the Intermediate Frequency (IF) bandwidth on the GNSS signal tracking enabling improvements of more than 50% quality.

A RF receiver frontend for SC-UWB in a 0.18-μm CMOS process

A radio frequency (RF) receiver frontend for single-carrier ultra-wideband (SC-UWB) is presented. The front end employs direct-conversion architecture, and consists of a differential low noise amplifier (LNA), a quadrature mixer, and two intermediate frequency (IF) amplifiers. The proposed LNA employs source inductively degenerated topology. First, the expression of input impedance matching bandwidth in terms of gate-source capacitance, resonant frequency and target S11 is given. Then, a noise figure optimization strategy under gain and power constraints is proposed, with consideration of the integrated gate inductor, the bond-wire inductance, and its variation. The LNA utilizes two stages with different resonant frequencies to acquire flat gain over the 7.1–8.1 GHz frequency band, and has two gain modes to obtain a higher receiver dynamic range. The mixer uses a double balanced Gilbert structure. The front end is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.43 mm2. In high and low gain modes, the measured maximum conversion gain are 42 dB and 22 dB, input 1 dB compression points are −40 dBm and −20 dBm, and S11 is better than −18 dB and −14.5 dB. The 3 dB IF bandwidth is more than 500 MHz. The double sideband noise figure is 4.7 dB in high gain mode. The total power consumption is 65 mW from a 1.8 V supply.

A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-μm CMOS process

A fully integrated multi-mode multi-band directed-conversion radio frequency (RF) receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented. The front-end employs direct-conversion design, and consists of two differential tunable low noise amplifiers (LNA), a quadrature mixer, and two intermediate frequency (IF) amplifiers. The two independent tunable LNAs are used to cover all the four frequency bands, achieving sufficient low noise and high gain performance with low power consumption. Switched capacitor arrays perform a resonant frequency point calibration for the LNAs. The two LNAs are combined at the driver stage of the mixer, which employs a folded double balanced Gilbert structure, and utilizes PMOS transistors as local oscillator (LO) switches to reduce flicker noise. The front-end has three gain modes to obtain a higher dynamic range. Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface (SPI) module. The front-end is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.3 mm2. The measured double-sideband (DSB) noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply.

A CMOS adaptive RF front-end receiver for wireless applications

Design and implementation of an image-rejection double-quadrature radio frequency front-end receiver based on tunable polyphase filters (PPF) are presented in this article. The front-end consists of two sets of PPFs and a double-quadrature down-converter. The design contains devices that allow process spread and frequency drift control, making it suitable for multi-standard applications. Formal analysis and statistical method leading to the polyphase filter optimal sizing have been dealt with in this article. The effects of parasitic capacitances and component mismatch are also considered and discussed. Steps within CMOS polyphase filter design flow are then provided to guarantee high image rejection ratio (IRR) performance. The front-end receiver exhibits more than 60 dB IRR and good linearity in high-frequency applications.

Computer-Aided Optimization of a 5.8 GHz ETC Receiver Front-End Design Using Memetic Algorithm

Systematic level design and optimization of a Radio Frequency (RF) receiver is a multi-dimensional problem and it is usually an arduous and experience-based work because of the trade-off between various system parameters. In the mean while, co-operated with Genetic Algorithm (GA) and local search, Memetic Algorithm (MA) gradually becomes popular to solve multi-dimensional optimization problems, and it can be an efficient method for computer-aided design of RF receivers. In this paper, the MA method was adopted to aid the design of a 5.8 GHz RF receiver front-end. The transfer function for the signal-to-noise ratio at the front-end output (SNRout) was first derived based on the gain, noise figure and inter-modulation product of each individual circuit component, and the transfer function was then used as the required fitness function for the MA method. The efficacy of the proposed method was validated by ADS simulations.

A transformer-loaded receiver front end for 2.4 GHz WLAN in 0.13 μm CMOS technology

A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented. Based on zero-IF receiver architecture, the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer. As the load of the LNA, the on-chip transformer is optimized for lowest resistive loss and highest power gain. The whole front end draws 21 mA from 1.2 V supply, and the measured results show a double side band noise figure of 3.75 dB, −31 dBm IIP3 with 44 dB conversion gain at maximum gain setting. Implemented in 0.13 μm CMOS technology, it occupies a 0.612 mm2 die size.

A 5.25-GHz image rejection RF front-End Receiver With Polyphase filters

A 5.25-GHz image rejection (IR) radio frequency (RF) front-end receiver is proposed, which is implemented in 0.18-μm CMOS technology. The proposed receiver adopts both a high-intermediate frequency (IF) and the double quadrature architecture to achieve high IR at 5-GHz frequency. The measured results show a power gain of 14 dB, a minimum noise figure of 7.9dB, and IIP3 of -8dBm. The measured maximum image rejection ratio is 45dBc. The receiver consumes a total of 32mA from a 1.8-V supply.