Radio Frequency Complementary Metal Oxide Semiconductor Research Articles

Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs

This paper describes a pioneering methodology to design, optimize, and reduce the total gate area of robust Operational Transconductance Amplifiers (OTAs). The Single-Ended Single-Stage (SESS) OTA has been chosen to validate the proposed technique by using the 180 nm planar Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technology. The Electronic Design Automationtool, named iMTGSPICE, was used to design and optimize the SESS OTA. There are several heuristics optimization techniques of Artificial Intelligence to optimize analog and radio-frequency CMOS ICs, but we have selected to use the Genetic Algorithm because it presents the best optimization performance among the other algorithms previously studied. This paper also describes a procedure of converting the Conventional planar MOSFETs (rectangular gate shape) into the Diamond MOSFETs (hexagonal gate shape) with the same electrical performance. Furthermore, it is proposed a procedure to simulate the Diamond MOSFETs (DMs) in the Simulation Program with Integrated Circuit Emphasis (SPICE) because there is still no SPICE model to perform the DM. Additionally, this work proposes a methodology to layout OTAs with Diamond MOSFETs, regarding different values of aspect ratios. The main result of this work reveals a total gate area reduction of approximately 30% of a robust OTA implemented with Diamond MOSFETs, with an alpha angle (α) equal to 45°, with respect to the one observed in the robust OTA implemented with standard MOSFETs, maintaining practically the same electrical performance and robustness.

Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

This article describes an experimental comparative study of the matching between the Octo conventional (octagonal gate geometry) and Conventional (rectangular gate shape) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) Integrated Circuits (ICs) technology and exposed to different X-rays Total Ionizing Doses (TIDs), under the on-state bias conditions. The results indicate that the Octo layout style with alpha ( $\alpha $ ) angle equal to 90° and a cut factor of 50% for MOSFETs is capable of boosting the device matching by at least 56.1%, on average, regarding the electrical parameters studied (Threshold Voltage and Subthreshold Swing), as compared to those found in the Conventional MOSFET counterparts, considering that they present the same bias conditions and regarding different TIDs. This happens due to the Longitudinal Corner Effect (LCE), Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) which are present in the Octo MOSFETs. Therefore, the Octagonal layout style can be considered as an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS ICs applications.

Analysis and design of a new low‐phase noise and Gm‐enhanced class‐C quadrature VCO

This study presents a new low-power and low-phase noise Colpitts quadrature voltage-controlled oscillator (QVCO). The proposed QVCO contains two differential Colpitts voltage-controlled oscillators (VCOs) that use gain-boosting technique to enhance the negative transconductance and relax start-up condition. Both switching and tail transistors are configured in class-C to improve impulse sensitivity function and phase noise performance of the circuit via better noise modulation function. In addition, flicker noise would be reduced because of the switched-biasing mechanism of tail transistors. Phase noise analysis shows that changing the bias voltage of switching as well as tail transistors can improve the phase noise performance of the core VCO with overlap reduction of the transistors active time. Consequently, due to no extra noisy elements for coupling and class-C biasing of all transistors, low-phase noise quadrature signals are generated. To verify the performance of the proposed technique, post-layout simulation is performed in Taiwan Semiconductor Manufacturing Company (TSMC) of 0.18 μm Radio Frequency-Complementary Metal-Oxide- Semiconductor (RF-CMOS) process at a supply voltage of 1.2 V. Post-layout simulation results show that the phase noise of the proposed QVCO is −120.6 dBc/Hz at 1 MHz offset from 5.73 GHz operation frequency. The total power consumption of the QVCO is 3.1 mW and the tuning range is from 5 to 5.73 GHz.

Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

This paper describes an experimental comparative study of the matching between conventional (rectangular gate shape) and Diamond (hexagonal gate geometry) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with alpha () angle equal to 90˚ for MOSFETs is capable of boosting the device matching by at least 17% regarding the electrical pa-rameters studied (Threshold Voltage and Subthreshold Slope) as compared with the conventional MOSFET counterparts, considering that they present the same gate area, channel width, bias conditions and for the same TID. This is due to the Longitudinal Corner Effect (LCE). Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) present in the structure of Diamond MOSFETs. Therefore, the Diamond layout style can be consid-ered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS inte-grated circuits (ICs) applications.

A new tail-switching superharmonic multiphase LC-VCO

PurposeMultiphase and quadrature voltage-controlled oscillators (QVCOs) play key roles in modern communication systems and their phase noise performance affects the performance of the overall system. Different studies are devoted to efficient quadrature signals generation. This paper aims to present a new low-phase noise superharmonic injection-locked QVCO.Design/methodology/approachThe proposed QVCO is comprised of two identical inductor-capacitor circuit (LC)-voltage-controlled oscillators (VCOs) in which second harmonics, with 180° phase shift, are injected from one core VCO to the gate of tail current source of the other VCO via a coupling capacitor. Using second harmonics with high amplitude will switch the tail from the inversion to the accumulation, and therefore, flicker noise is reduced. Also, because of the use of lossless and noiseless coupling elements, that is, coupling capacitors, and also because of the existence of an inherent high-pass filter, the proposed LC-QVCO has a good phase noise performance.FindingsThe introduced technique is designed and simulated in a commercial 0.18 µm radio frequency complementary metal oxide semiconductor (RF-CMOS) technology and 10 dB improvement of close-in phase noise is achieved (compared to the conventional method). Simulation results show that the phase noise of the proposed QVCO is −130.3 dBc/Hz at 3 MHz offset from 5.76 GHz center frequency, while the total direct current (DC) current drawn from a 0.9-V power supply is 4.25 mA (figure of merit = −190.2 dBc). Monte Carlo simulation results show that the figure of merit of the circuit has a Gaussian distribution with mean value and standard deviation of −189.97 dBc and 0.183, respectively.Originality/valueThis technique provides a new simple but efficient superharmonic coupling and noise shaping method that reduces close-in phase noise of superharmonic multiphase VCOs by switching of tail transistors with 2 ω0 (second harmonic of oscillation frequency). No extra devices such as area-consuming transformer or additional power-hungry oscillator are used for coupling.

Wafer-scalable, aligned carbon nanotube transistors operating at frequencies of over 100 GHz

Wireless device technology operating in the millimetre-wave regime (30 to 300 GHz) increasingly needs to offer both high performance and a high level of integration with complementary metal–oxide–semiconductor (CMOS) technology. Aligned carbon nanotubes are proposed as an alternative to III–V technologies in such applications because of their highly linear signal amplification and compatibility with CMOS. Here we report the wafer-scalable fabrication of aligned carbon nanotube field-effect transistors operating at gigahertz frequencies. The devices have gate lengths of 110 nm and are capable, in distinct devices, of an extrinsic cutoff frequency and maximum frequency of oscillation of over 100 GHz, which surpasses the 90 GHz cutoff frequency of radio-frequency CMOS devices with gate lengths of 100 nm and is close to the performance of GaAs technology. Our devices also offer good linearity, with distinct devices capable of a peak output third-order intercept point of 26.5 dB when normalized to the 1 dB compression power, and 10.4 dB when normalized to d.c. power. Radio-frequency transistors made from aligned carbon nanotubes offer high linearity and an extrinsic cutoff frequency of over 100 GHz.

Adaptive Body Biasing Circuit for Reliability and Variability Compensation of a Low Power RF Amplifier

This paper presents a simple compensation biasing circuit to enhance the reliability and variability of the low-power radio-frequency (RF) amplifier. The compensation function is achieved through a threshold voltage adjustment, which is realized by an adaptive varying body voltage of power amplifier transistors. The proposed circuit effectively preserves the power amplifier performance over a wide level range of output power under threshold voltage shift and electron mobility degradation. At the 0.63 dBm output power level, the sensitivity of the normalized efficiency of the power amplifier with the proposed compensation circuit under 0.16% threshold voltage shift and 0.16% mobility variations decreases as nearly 6.7 times and 2 times compared to the power amplifier without the compensation circuit, respectively. The operational principle of this structure is studied by deriving the analytical equations. The post-layout simulation results in the 180-nm RF complementary metal–oxide–semiconductor process are obtained and verify the proposed circuit effectiveness.

Nanoelectronic COupled Problems Solutions: uncertainty quantification for analysis and optimization of an RFIC interference problem

The FP7 project nanoCOPS (the 7th Framework Programme project Nanoelectronic COupled Problems Solutions) derived new methods for simulation during development of designs of integrated products. It has covered advanced simulation techniques for electromagnetics with feedback couplings to electronic circuits, heat and stress. It was inspired by interest from semiconductor industry and by a simulation tool vendor in electronic design automation.Due to the application of higher frequencies and the continuous down-scaling process, there is a higher probability of unforeseen interactions between different domains of a Radio Frequency Integrated Circuit (RFIC), which can lead to the variability of the output performance functions. Since these undesired phenomena ought to be investigated in the early phases of the integrated circuit (IC) design, in this work we formulate the robust optimization problem in terms of the expectation and the standard deviation values under the uncertainties of material parameters.Therein, the statistical information included in the multi-objective functional can be provided by a response surface model. For this purpose the Stochastic Collocation Method (SCM) combined with Polynomial Chaos Expansion (PCE) has been used. The reason for analyzing the variability of the Electromagnetic Interference (EMI) is, on the one hand, to quantify the uncertainty in an integrated Radio-Frequency Complementary Metal-Oxide Semi-Conductor (RFCMOS) transceiver design, and, on the other hand, to improve this design in a robust sense. We have illustrated our methodology for an integrated Radio-Frequency Complementary Metal-Oxide Semi-Conductor (RFCMOS) transceiver design.

Power dividers based simplified design topology for planar microwave I-Q mixers

ABSTRACTA simplified design topology for realising planar microwave I-Q mixers is proposed in this article. Conventional I-Q mixers utilise hybrids, vias, cross over or wire-bonds for realisation. The reported design is based on a unique arrangement of six radio frequency (RF) power dividers with simpler routing for attaining similar performances for 10% RF bandwidth and fixed local oscillator (LO) frequency. The proposed topology is demonstrated by realising a mixer at 13.5 GHz in microwave integrated circuit (MIC) technology. With +10 dBm LO power, the measured maximum RF-I and RF-Q conversion loss is 13 dB and amplitude and phase imbalances are 0.1 dB root mean square (RMS) and 4.7° RMS over 1000 MHz bandwidth. The design topology is generic and can be used for any frequency band and technology (MIC, monolithic microwave integrated circuit, RF complementary metal oxide semiconductor etc.).

2.7–4.0 GHz PLL with dual-mode auto frequency calibration for navigation system on chip

A 2.7–4.0 GHz dual-mode auto frequency calibration (AFC) fast locking PLL was designed for navigation system on chip (SoC). The SoC was composed of one radio frequency (RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator (VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop (PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor (CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is −90 dBc/Hz@100 kHz frequency offset and −120 dBc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about −142 dBm and −155 dBm, respectively. The area of the proposed PLL is 0.35 mm2 and the total SoC area is about 9.6 mm2.

0.9–10.6 GHz UWB mixer using current bleeding for multi‐band application

A complementary metal oxide semiconductor (CMOS) downconversion mixer for ultra-wideband (UWB) applications is presented. The mixer circuit is designed using a VIS 0.25 μm radio frequency (RF) CMOS technology, working at the 0.9-10.6 GHz frequency range; it will be used in applications such as IEEE wireless fidelity (Wi-Fi), global systems for mobile (GSM) and worldwide interoperability for microwave access (WiMAX). The core of the mixer has been designed based on double-balanced cell architecture, and uses the current-bleeding method to increase the linearity and improve the conversion gain. A resistor is put on the drain of the MOS between two RF inputs, which will improve the flatness of the conversion gain. The measured conversion gain of the mixer is 8.6 ± 1 dB. The 1 dB compression point of the intermediate frequency (IF) output power is equal to -8 dBm. The RF and the local oscillator (LO) input return loss are well below -9 dB. The noise figure is 13.1 dB, whereas the IF is 100 MHz, and the mixer core dissipates 9.8 mW under a 1.8 V supply. The analytical, simulated and measured results are mutually consistent.

Low power current-mode voltage controlled oscillator for 2.4 GHz wireless applications

In this paper, a new Complementary Metal Oxide Semiconductor (CMOS) low power Quadrature Voltage Controlled Oscillator (QVCO) based on Chartered 0.18μm Radio frequency (RF) CMOS technology for 2.4GHz IEEE 802.11b Wireless Local Area Networks (WLAN) applications is presented. Two explicit quadrature outputs can be realized at high impedance terminals of the QVCO, and it can be cascaded directly to the next stage of a communication system without any matching conditions. The post-layout simulation results show that the oscillation frequency of the QVCO can be tuned from 1.8GHz to 2.4GHz by changing the control voltage.

Electromagnetic Characteristics of a Novel Radio-Frequency Complementary Metal–Oxide–Semiconductor Active Inductor

This paper presents a novel radio-frequency (RF) complementary metal-oxide-semiconductor (CMOS) active inductor for the design of RF integrated circuits (RFICs). The electromagnetic characteristics of the RF CMOS gyrator-based active inductor were investigated. The RF CMOS gyrator-based active inductor utilized a loss compensation circuit to produce equivalent negative resistance and compensate for the loss of transistors and bias circuitry. The proposed active inductor realized both high-inductance and high-quality factor. The quality factor was greater than 10 from 2.5 to 3.5 GHz. The maximum quality factor was 76.2. The active inductor was applied to the design of a microwave notch filter. The active notch filter with the RF CMOS gyrator-based active inductor was able to reject microwave image signals for modern wireless communication systems.

A K-Band CMOS Phase Shifter MMIC Based on a Tunable Composite Metamaterial

This letter presents a K-band phase shifter monolithic microwave integrated circuit (MMIC) which is based on electrically tunable composite left- and right-handed metamaterials. This structure utilizes both positive and negative phase shifting metamaterial characteristics to allow for a wide tuning range. This is achieved by varying both the capacitance and inductance of the metamaterial structure. The inductance tuning is realized by an improved active inductor with a self-resonant frequency greater than 20 GHz. The phase shifter is divided into four sections of unit cell metamaterial and is implemented in 0.13 μm radio frequency complementary metal-oxide-semiconductor (RFCMOS) technology. The phase shifter exhibits a continuous phase tuning range of 121° (from -80° to +41°) and 136° (from -120° to + 16°) at 21.5 and 22.5 GHz, respectively. The minimum insertion loss is -10.1 and -10.5 dB at 21.5 and 22.5 GHz, respectively. At 26 GHz, a wide phase shift of greater than 300° is achieved in a compact chip area of 0.28 mm2.

Novel base station radio technologies for third-generation wireless applications

In this paper, we address novel base station radio architectures with emphasis on radio frequency (RF) integration for multi-carrier operation. Radio architectures and device technologies that influence the system performance for wideband signal transport have been discussed. We have shown that a direct conversion transmitter with a digital intermediate frequency (DIF) receiver architecture is the most effective architecture for new base station radio implementation. The recently developed high performance silicon germanium-heterojunction bipolar transistor (SiGe-HBT) and RF complementary metal oxide semiconductor (CMOS) technologies are promising to be suitable for RF integration in multichip modules or integrated circuit (IC) formats for deployment in base station radios.

Full software analysis and impedance matching of radio frequency CMOS integrated circuits

We present a systematic analysis technique of complementary metal-oxide-semiconductor (CMOS) radio-frequency (RF) integrated circuits (ICs). A full simulation program with integrated circuit emphasis (SPICE) simulation of the whole chip including the package and the die, with the parameters extracted from purely software analysis, has been performed. It is shown that the RF impedance matching without S-parameter based techniques is possible and the measured results agree well with our SPICE-only software based technique.