The III-V/Ge complementary-FinFET (C-FinFET) based integrated circuits are more susceptible to radiation-induced single event transients (SET) than silicon counterparts. In this paper, the single event transients in n-channel InGaAs structures such as stacked 5-fin InGaAs-Bulk, InGaAs-Body on Insulator (InGaAs-BOI) and InGaAs-on-Insulator (InGaAs-OI) FinFETs are analyzed and optimized for SET-tolerant InGaAs/Ge-OI C-FinFET circuits. The SET analysis is done for these structures for different Linear Energy Transfer (LET), vertical strike positions, normal/angular strike incidences, gate underlap/overlap and oxide materials. The SET pulse widths for InGaAs/Ge-OI C-FinFETs are determined for different load capacitances, LETs, supply voltages and PMOS ON current. It is observed that the SET pulsewidth is lesser for InGaAs-OI/Ge-OI C-FinFETs compared to other two chosen structures. However, having the advantages of both InGaAs-Bulk and InGaAs-OI structures, the InGaAs-BOI FinFET with lesser pulsewidth than InGaAs-Bulk FinFET is a better candidate to use in radiation-prone environment.