Quantum-well Field-effect Transistors Research Articles

Asymmetric Doping‐Dependent Electron Transport Mobility in InxGa1–xAs/GaAs Quantum Well Field‐Effect Transistor Structure

We analyze the asymmetric doping‐dependent electron mobility μ of GaAs/InGaAs/GaAs quantum well field‐effect transistor (QWFET) structure. We consider doping concentrations, nd1 and nd2, in the substrate and surface barriers, respectively, and study μ as a function of nd2, taking (nd1 + nd2) unchanged. An increase in nd2 decreases nd1, yielding interesting changes in the occupation of subbands. For well width W < 164 Å, μ is due to single subband occupancy (SSO). Around W = 164 Å, there occurs first SSO, then double subband occupancy (DSO), and again SSO with an increase in nd2. Near the transition of subbands, abrupt discontinuities in μ arise due to inter‐subband effects. Thus, high to low and then high values of μ are obtained, displaying almost flat‐like variations, symmetric about |nd2 − nd1| = 0. As W becomes wider, complete DSO occurs throughout the range of nd2 having reduced μ. Alternatively, keeping nd1 unchanged and by increasing nd2, μ raises due to enhanced N s , with a drop near the transition from SSO to DSO. Under SSO, μ is controlled by the ionized impurity and alloy disorder scatterings, while under DSO, the impurity scattering determines μ. Our analysis on μ can help to examine the inter‐subband effects on device characteristics of the QWFET system.

Doping-Dependent Nonlinear Electron Mobility in GaAs|InxGa1 –xAs Coupled Quantum-Well Pseudo-Morphic MODFET Structure

We analyze the asymmetric delta-doping dependence of nonlinear electron mobility μ of GaAs|InxGa1 –xAs double quantum-well pseudo-morphic modulation doped field-effect transistor structure. We solve the Schrodinger and Poisson’s equations self-consistently to obtain the sub-band energy levels and wave functions. We consider scatterings due to the ionized impurities (IMP), alloy disorder (AL), and interface roughness (IR) to calculate μ for a system having double sub-band occupancy, in which the inter-sub-band effects play an important role. Considering the doping concentrations in the barriers towards the substrate and surface sides as Nd1 and Nd2, respectively, we show that variation of Nd1 leads to a dip in μ near Nd1 = Nd2, at which the resonance of the sub-band states occurs. A similar dip in μ as a function of Nd1 is also obtained at Nd1 = Nd2 by keeping (Nd1 + Nd2) unchanged. By increasing the central barrier width and well width, the dip in μ becomes sharp. We note that even though the overall μ is governed by the IMP- and AL-scatterings, the dip in μ is mostly affected through substantial variation of the sub-band mobilities due to IR-scattering near the resonance. Our results of nonlinear electron mobility near the resonance of sub-band states can be utilized for the performance analysis of GaAs|InGaAs pseudo-morphic quantum-well field-effect transistors.

Three-dimensional analytical modeling for small-geometry AlInSb/AlSb/InSb double-gate high-electron-mobility transistors (DG-HEMTs)

A simple physics-based three-dimensional (3-D) analytical model for AlInSb/AlSb/InSb double-gate high-electron-mobility transistors (DG-HEMTs) is presented. The model accurately predicts the short-channel effects (SCEs) in the channel region for various device dimensions, viz. channel length and width, by solving the three-dimensional Poisson equation. The effects of the barrier layer (AlInSb) thickness and the high doping concentration on the threshold voltage are also considered. Analytical expressions for the surface potential and threshold voltage are derived, and the analytical results closely match those obtained from Sentaurus technology computer-aided design (TCAD) simulations. The drain current and transconductance of the AlInSb/AlSb/InSb double-gate HEMT device are compared with experimental data obtained for a quantum-well field-effect transistor (QWFET). The proposed AlInSb/AlSb/InSb double-gate HEMT shows excellent properties for use in high-speed and low-power applications.

Doping-Dependent Nonlinear Electron Mobility in GaAs|In-=SUB=-x-=/SUB=-Ga-=SUB=-1-x-=/SUB=-As Coupled Quantum-Well Pseudo-Morphic MODFET Structure

We analyze the asymmetric delta-doping dependence of nonlinear electron mobility μ of GaAs|InxGa1-xAs double quantum-well pseudo-morphic modulation doped field-effect transistor structure. We solve the Schrodinger and Poisson's equations self-consistently to obtain the sub-band energy levels and wave functions. We consider scatterings due to the ionized impurities (IMP), alloy disorder (AL), and interface roughness (IR) to calculate μ for a system having double sub-band occupancy, in which the inter-sub-band effects play an important role. Considering the doping concentrations in the barriers towards the substrate and surface sides as Nd1 and Nd2, respectively, we show that variation of Nd1 leads to a dip in μ near Nd1=Nd2, at which the resonance of the sub-band states occurs. A similar dip in μ as a function of Nd1 is also obtained at Nd1=Nd2 by keeping (Nd1+Nd2) unchanged. By increasing the central barrier width and well width, the dip in μ becomes sharp. We note that even though the overall μ is governed by the IMP- and AL-scatterings, the dip in μ is mostly affected through substantial variation of the sub-band mobilities due to IR-scattering near the resonance. Our results of nonlinear electron mobility near the resonance of sub-band states can be utilized for the performance analysis of GaAs|InGaAs pseudo-morphic quantum-well field-effect transistors. Keywords: asymmetric double quantum wells, GaAs|InxGa1-xAs structures, nonlinear electron mobility, pseudo-morphic HEMT structures, resonance of sub-band states.

Design and Performance Analysis of Depletion-Mode InSb Quantum-Well Field-Effect Transistor for Logic Applications

The design of a 1[Formula: see text][Formula: see text]m gate length depletion-mode InSb quantum-well field-effect transistor (QWFET) with a 10[Formula: see text]nm-thick Al2O3 gate dielectric has been optimized using a quantum corrected self-consistent Schrödinger-Poisson (QCSP) and two-dimensional drift-diffusion model. The model predicts a very high electron mobility of 4.42[Formula: see text]m2V[Formula: see text]s[Formula: see text] at [Formula: see text][Formula: see text]V, a small pinch off gate voltage ([Formula: see text]) of [Formula: see text]0.25[Formula: see text]V, a maximum extrinsic transconductance ([Formula: see text]) of [Formula: see text][Formula: see text]4.85[Formula: see text]mS/[Formula: see text]m and a drain current density of more than 3.34[Formula: see text]mA/[Formula: see text]m. A short-circuit current-gain cut-off frequency ([Formula: see text]) of 374[Formula: see text]GHz and a maximum oscillation frequency ([Formula: see text]) of 645[Formula: see text]GHz are predicted for the device. These characteristics make the device a potential candidate for low power, high-speed logic electronic device applications.

Microwave detection performance of In 0.53 Ga 0.47 As/GaAs 0.5 Sb 0.5 quantum‐well tunnel field‐effect transistors

The performance of In0.53Ga0.47As/GaAs0.5Sb0.5 quantum-well tunnel field-effect transistors (TFETs) for microwave-frequency detection is explored experimentally. The strong nonlinearity of the TFET transfer characteristic, which arises from a combination of band-to-band tunnelling between source and channel and gate modulation of the tunnel junction, can be utilised for high-sensitivity microwave detection. Using an analytical model, it is shown that TFET detection current sensitivity is approximately proportional to the second-order derivative of the transfer current-voltage characteristic. Though unoptimised, the large-area TFET detectors evaluated experimentally exhibit an unmatched voltage sensitivity of 112 kV/W, an impedance-matched noise equivalent power of 7.0 pW/Hz0.5, and a bandwidth of 4 GHz. The microwave detection performance of TFETs can be enhanced by mitigating parasitic effects, improving the semiconductor/oxide interface quality, and scaling the gate area.

Optimized Novel Indium Antimonide Quantum Well Field Effect Transistor for High-Speed and Low Power Logic Applications

The physical gate length L G of the Si transistors are shrinking day by day to meet Moore’s law that states the number of transistors per integrated circuit doubles in every 24 months. It is projected that L G may be down to ~20 nm. Therefore, it is urgent need to be “energy efficient” which operates with the lowest switching power. Much effort has been paid to incorporate III-V nanoelectronics on the silicon platform due to highest intrinsic electron mobility. The InSb quantum well field effect transistor (QWFET) is a promising candidate for future high performance and low power logic applications [1,2]. In addition, recent success in depositing high-quality Al2O3 gate dielectrics by atomic layer deposition (ALD) on the InSb quantum wells (QWs) and completely depletion of the two-dimensional electron gas (2DEG) confined in InSb QW opens the prospects to fabricate high-quality InSb QW field effect transistor (FET) [3,4]. An InSb QWFET with a 10 nm thick Al2O3 top gate insulator has been simulated by using quantum corrected Schrödinger-Poisson (QCSP) solution as shown in Fig. 1 (a). Gate voltage (V g) dependent electron density (ns ) and mobility (µ) is shown in Fig. 1 (b). A very high electron mobility 4.42 m2V-1s-1 at V g= 0V is achieved which is at least ~180 times greater than that of Si NMOS. The confined 2DEG in InSb QW is completely depleted with a very small V g= -0.25V (is called as the pinch–off voltage, V p). The slope of the ns-Vg yields a giant gate controllability ratio of dn s/dV g = ~ 5.2 × 1015 m -2 V -1 (estimated in the range of V g=-0.2V to 0V). The room temperature conduction band (CB) and valance band (VB) profile of the proposed structure at V g= 0 and -0.25V are calculated by QCSP as shown in Fig. 2. The QW is lifted above the Fermi level (E F) at V g = -0.25V which is confirmed complete depletion (V p) as shown in Fig. 1. Moreover, the hole accumulation prevents as the VB doesn’t touch the E F. The interface trap density (D it) has been calculated using the equation D it= -(dQ it / (e × d(E F - E V))) where Q it is the net charge (difference between oxide and semiconductor charge) [4]. Energy dependent D it and corresponding applied gate voltage (V g) is shown in Fig. 3. Very low D it is found to be 7.8 × 1014 – 3.7 × 1016 m-2eV- 1 at the interface between Al2O3 and Al0.1In0.9Sb top layer of the InSb QWFET, results a giant dn s/dV g (Fig. 1b). It indicates that the E F is smoothly tuned by the V g due to a very low D it of the InSb QWFET. The capacitance-voltage (C-V) calculation has also been confirmed the low D it and V p of the proposed QWFET. The standard transistor characteristics with I D versus V DS at different V g, transconductance (g m) have also been calculated and explained by the established theory and experimental explanation. [1] T. Ashley et al. Proceedings 7th International Conference on Solid-State and Integrated Circuits Technology (SSICT), 2253 (2004). [2] S. Datta, Microelectronic Engineering84, 2133 (2007). [3] M. M. Uddin et al., Appl. Phys. Lett.101, 233503 (2012). [4] M. M. Uddin et al., Appl. Phys. Lett.103, 123502 (2013). Fig. 1: (a) Cross section of InSb optimized QWFET layer structure with LG =100 nm and δ-doping (dashed line). (b) Electron density (n s) and mobility (μ) of the InSb QWFET as a function of gate bias (V g) at 300 K. The dashed line points to the pinch-off voltage V p. Fig. 2: Band profile (CB and VB) of the proposed InSb QWFET at 300 K. The Fermi level is shown at 0eV. Fig. 3: The interface trap density (D it) as a function of E F-E V obtained from the QCSP solution with corresponding applied V g (V). Figure 1

Ultralow Resistance Ohmic Contacts for p-Channel InGaSb Field-Effect Transistors

We demonstrate ultralow ohmic contact resistance to antimonide-based, p-channel quantum-well field-effect transistor (QW-FET) structures using a new p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">±</sup> -InAs/InAsSb cap structure. The incorporation of a p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">±</sup> -InAsSb layer enables the use of a thicker cap with lower sheet resistance, resulting in an improved contact resistivity. Using a Pd-based ohmic scheme, the composite cap structure resulted in a 4x reduction in contact resistance compared with a standard p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">±</sup> -InAs cap. This translates into nearly 3x improvement in the gm of fabricated InGaSb p-channel QW-FETs. Furthermore, Ni contacts on the composite cap were fabricated and a contact resistance of 45 Ω · μm was obtained. An accurate contact resistivity extraction in this very low range is possible through nanotransmission line models with sub-100 nm contacts. In devices of this kind with Ni-based contacts, we derive an ultralow contact resistivity of 5.2 · 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> Ω · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

(Invited) Monolithic Integration of III-V As- and P-Based Devices on Si through Direct MBE Growth and Using Lattice Engineered Substrates

Mainstream silicon (Si) CMOS technology is finally experiencing limitations of pure Si-based material and process. For digital electronics, to extend Moore’s law, the industry increasingly is investigating alternative materials and technologies to enhance channel transport properties and reduce power dissipation for future generation transistor circuitry. Heterogeneous integration of compound III-V semiconductor devices on Si may realize high performance integrated circuits for analog and digital applications and can incorporate optoelectronic components for high-speed data transfer. Such integration provides the combined advantages of high volume production of Si-based electronic circuitry with superior high-speed performance of III-V components. At IQE, we developed molecular beam epitaxy (MBE) growth processes for the production of high quality III-V based transistor structures monolithically integrated onto CMOS-compatible substrates by direct MBE growth on Si wafers and also by utilization of specialized Si-on-Lattice-Engineered-Substrate (SOLES) substrates. Through work with industry partners, IQE has grown InP-based high electron mobility transistor (HEMT) and quantum well field effect transistor (QWFET) structures directly on Si substrates by MBE. Following a high-K gate dielectric fabrication process, QWFET devices demonstrated high transconductance of 1750μS/μm and high drive current of 0.49mA/μm at VDS=0.5V. [1] As part of a program funded by the US Defense Advanced Research Projects Agency, IQE developed a direct MBE growth approach of an InP-based heterojunction bipolar transistor (HBT) structure on the SOLES substrates, and together with our collaborators successfully created clusters of high-speed III-V HBT circuitry monolithically integrated side-by-side with Si CMOS on the same wafer. [2] In this paper, we will discuss structural and electronic properties of epitaxial device material, including dislocation filtering in the mismatched metamorphic buffers, and compare performance of devices fabricated on Si with reference material grown on lattice-matched InP substrates. [1] Radosavljevic, M.; Chu-Kung, B.; Corcoran, S.; Dewey, G.; Hudait, M. K.; Fastenau, J. M.; Kavalieros, J.; Liu, W. K.; Lubyshev,D.; Metz, M.; Millard, K.; Mukherjee, N.; Rachmady, W.; Shah, U.; Chau, R. (2009), IEDM Tech. Dig., p.13.1. [2] W. K. Liu, D. Lubyshev, J. M. Fastenau, Y. Wu, M. T. Bulsara, E. A. Fitzgerald, M. Urteaga, W. Ha, J. Bergman, B. Brar, W. E. Hoke, J. R. LaRoche, K. J. Herrick, T. E. Kazior, D. Clark, D. Smith, R. F. Thompson, C. Drazek, and N. Daval, J. Crystal Growth, 311, 1979 (2009).

Performance analysis of InSb based QWFET for ultra high speed applications

An indium antimonide based QWFET (quantum well field effect transistor) with the gate length down to 50 nm has been designed and investigated for the first time for L-band radar applications at 230 GHz. QWFETs are designed at the high performance node of the International Technology Road Map for Semiconductors (ITRS) requirements of drive current (Semiconductor Industry Association 2010). The performance of the device is investigated using the SYNOPSYS CAD (TCAD) software. InSb based QWFET could be a promising device technology for very low power and ultra-high speed performance with 5–10 times low DC power dissipation.

Enhancing p-channel InGaSb QW-FETs via Process-Induced Compressive Uniaxial Strain

We study the effect of process-induced uniaxial stress on the performance of biaxially strained InGaSb p-channel quantum-well field-effect transistors (QW-FETs). Uniaxial stress is incorporated using a self-aligned nitride stressor. Compared with unstressed control devices, fabricated stressed devices with a gate length of L g =0.30 μm showed an increase of more than 40% in the drain current at V GS -V T =-0.5 V and V DS = -2.0\) V, an enhancement of more than 40% in the peak extrinsic transconductance at V DS = -2.0\) V, and a reduction in the source and drain resistance of 25%. These figures suggest an enhancement of the intrinsic transconductance by as much as 60%. The improvement in device characteristics was also found to scale favorably with gate length. The results indicate that process-induced compressive uniaxial strain holds great promise for developing high-performance antimonide-based p-FETs.

(Invited) The Materials Integration of Ge and InxGa1-X As on Si Template for Next Generation CMOS Applications

Lately, the semiconductor industry has paid a lot of attentions to the III-V compound semiconductor materials such as InSb, InxGa1-xAs for next generation CMOS applications, because these materials have significantly higher carrier mobility than silicon. For example, the electron mobility of InAs could reach 20000 cm2V-1s-1. High-speed devices such as quantum-well field-effect transistors (QWFETs) made from these III-V materials have demonstrated very low gate delay time. However, hole mobility for III-V materials are very low in general, some are even lower than the hole mobility of Si. So, it is important to look for a proper material with high hole mobility as p-channel FETs for future complementary CMOS architecture. Since Ge has a much higher bulk hole mobility (mh =1900 cm2/Vs) as compared to GaAs (mh = 400 cm2/Vs), Ge is suitable as p type channel material. Due to the small lattice mismatch (~0.08%) between GaAs and Ge, the integration of Ge with GaAs is comparable easy as compared to grow on Si , therefore thick Ge film can be grown as channel on GaAs substrates with very low defect density and integrate with InxGa1-xAs devices as a CMOS structure. In this talk, the growth of high quality Ge film on GaAs substrate by ultra high vacuum chemical vapor deposition (UHVCVD) and high quality InAs material on Ge/SiGe/Si template grown by molecular beam epitaxy (MBE) will be particularly reported. By the observation of XRD and AFM, both Ge film grown on GaAs material and InAs grown on Si substrates demonstrate high crystallinity and good surface morphology. The developed epitaxial materials systems including Ge on GaAs and InAs on Si are useful for future III-V/Ge/Si integration for next generation high speed low power CMOS application as well as for RF/digital mixed signal circuit application in the future.

Channel Thickness Dependence of InGaAs Quantum-Well Field-Effect Transistors With High- $\kappa$ Gate Dielectrics

We have studied channel thickness dependence of InGaAs quantum-well field-effect transistors (QWFETs) with high-κ gate dielectrics. Device performances of ultrathin 5- and 10-nm-channel In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As QWFETs with gate length down to sub-50-nm regime have been investigated. Thinning down the channel improves subthreshold characteristics and reduces the short-channel effect. The 5-nm In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As channel ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Lg</i> = 40 nm) devices exhibit a reduced subthreshold swing (SS) of around 100 mV/dec and drain-induced barrier lowering (DIBL) of 128 mV/V compared to 10-nm In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As channel devices (SS of ~ 140 mV/dec and DIBL of ~ 275 mV/V). However, the drawback for thinner channel devices is that the effective channel mobility also decreases. At inversion charge density of 3 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , 10-nm In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As channel devices exhibit mobility of 1860 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s versus mobility of 1460 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s for 5-nm In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As channel devices.

Experimental Study of $\langle \hbox{110}\rangle$ Uniaxial Stress Effects on p-Channel GaAs Quantum-Well FETs

The impact of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\langle \hbox{110}\rangle$</tex></formula> uniaxial stress on 2-D hole gas (2DHG) transport and charge control in a GaAs quantum well (QW) is studied through wafer bending experiments. Ungated Hall bars and QW field-effect transistors (FETs) were characterized under various stress levels. Through Hall measurements, changes in hole mobility and concentration due to applied stress were separated. The piezoresistance coefficients of the 2DHG along the two <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\langle \hbox{110} \rangle$</tex></formula> directions in the GaAs QW have been determined for the first time. We found that the linear-regime current of the QW-FET changes due to a combination of piezoelectric effect and hole mobility changes. The value of these coefficients suggests that uniaxial strain engineering is a viable technique to improve p-channel GaAs QW-FET performance for future logic applications.

Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs

A simulation methodology for ultra-scaled InAs quantum well field effect transistors (QWFETs) is presented and used to provide design guidelines and a path to improve device performance. A multiscale modeling approach is adopted, where strain is computed in an atomistic valence-force-field method, an atomistic sp3d5s* tight-binding model is used to compute channel effective masses, and a 2-D real-space effective mass based ballistic quantum transport model is employed to simulate three terminal current-voltage characteristics including gate leakage. The simulation methodology is first benchmarked against experimental I-V data obtained from devices with gate lengths ranging from 30 to 50 nm. A good quantitative match is obtained. The calibrated simulation methodology is subsequently applied to optimize the design of a 20 nm gate length device. Two critical parameters have been identified to control the gate leakage magnitude of the QWFETs, (i) the geometry of the gate contact (curved or square) and (ii) the gate metal work function. In addition to pushing the threshold voltage towards an enhancement mode operation, a higher gate metal work function can help suppress the gate leakage and allow for much aggressive insulator scaling.

Investigation of scalability of In 0.7Ga 0.3As quantum well field effect transistor (QWFET) architecture for logic applications

In this paper, the scalability of In 0.7Ga 0.3As QWFET is investigated using two-dimensional numerical drift–diffusion simulation. Numerical drift–diffusion simulations were calibrated using experimental results on short-channel In 0.7Ga 0.3As QWFETs [7] to include the effects of velocity overshoot. Logic figures of merit (sub-threshold slope, saturated threshold voltage, drain induced barrier lowering, I ON/ I OFF ratio over a specified gate swing, effective injection velocity and intrinsic switching delay) extracted from the numerical simulations are in excellent agreement with the experimental data. Three alternate QWFET device architectures are proposed and thoroughly investigated for 15 nm node and beyond logic applications. Amongst them, double-gate In 0.7Ga 0.3As QWFET shows the best scalability in terms of logic figures of merit, thus making it an ideal candidate for the design and demonstration of the ultimate scaled transistor.

Hole mobility enhancement in In0.41Ga0.59Sb quantum-well field-effect transistors

The impact of ⟨110⟩ uniaxial strain on the characteristics of p-channel In0.41Ga0.59Sb quantum-well field-effect transistors (QW-FETs) is studied through chip-bending experiments. Uniaxial strain is found to affect the linear-regime drain current and the threshold voltage of the FET through the modulation of the hole mobility of the two-dimensional hole gas (2DHG) in the QW-FET. The piezoresistance coefficients of the 2DHG have been determined to be π∥⟨110⟩=1.17×10−10 cm2/dyn and π⊥⟨110⟩=−1.9×10−11 cm2/dyn. The value of π∥⟨110⟩ is 1.5 times that of holes in Si metal-oxide-semiconductor (MOS) field-effect transistors and establishes InGaSb as a promising material system for a future III-V complementary MOS (CMOS) technology.

Small-Signal Response of Inversion Layers in High-Mobility $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ MOSFETs Made With Thin High- $\kappa$ Dielectrics

Ultrahigh-mobility compound semiconductor-based MOSFETs and quantum-well field-effect transistors could enable the next generation of logic transistors operating at low supply voltages since these materials exhibit excellent electron transport properties. While the long-channel In0.53 Ga0.47As MOSFETs exhibit promising characteristics with unpinned Fermi level at the InGaAs-dielectric interface, the high-field channel mobility as well as subthreshold characteristics needs further improvement. In this paper, we present a comprehensive equivalent circuit model that accurately evaluates the experimental small-signal response of inversion layers in In0.53 Ga0.47As MOSFETs fabricated with LaAlO3 gate dielectric and enables accurate extraction of the interface state profile, the trap dynamics, and the effective channel mobility.

DC and RF Performance Improvement of 70 nm Quantum Well Field Effect Transistor by Narrowing Source–Drain Spacing Technology

A 70 nm InAs channel quantum well field effect transistor (QWFET) fabricated by a narrowing source–drain (S/D) spacing technique was realized for future high-speed and logic applications. The S/D spacing was decreased from 3 to 0.65 µm through a simple fabrication process, which is an ameliorative redeposition ohmic technique. The drain-source current density and transconductance of the device were increased from 391 to 517 mA/mm and from 946 to 1348 mS/mm after the scaling of the S/D spacing, respectively. In addition, the current gain cutoff frequency ( fT) was also increased from 185 to 205 GHz. These results show that the easy method can effectively improve the III–V QWFET device performance for high-frequency and high-speed applications.

Growth of Strain InAs-Channel Quantum Well FETs on Si Substrate Using SiGe buffer

The growth of the AlGaSb/InAs quantum well field effect transistor(QWFET) epitaxial structure on the Si substrate has been investigated. Buffer layers consisted of UHV/chemical vapor deposited grown Ge/GeSi and molecular beam epitaxy-grown AlGaSb/AlSb/GaAs were used to accommodate the strain induced by the large lattice mismatch between the AlGaSb/InAs QWFET structure and the Si substrate. A very high room-temperature electron mobility of 27300 cm2 /V s was achieved. Strained QWFET was also grown on the GaAs substrate, it is found that the strained QWFET grown on the Si substrate has higher electron mobility due to high strain induced in this structure.