Quantum Error Correction Circuit Research Articles

Low-latency readout electronics for dynamic superconducting quantum computing

Dynamic quantum computing can support quantum error correction circuits to build a large general-purpose quantum computer, which requires electronic instruments to perform the closed-loop operation of readout, processing, and control within 1% of the qubit coherence time. In this paper, we present low-latency readout electronics for dynamic superconducting quantum computing. The readout electronics use a low-latency analog-to-digital converter to capture analog signals, a field-programmable gate array (FPGA) to process digital signals, and the general I/O resources of the FPGA to forward the readout results. Running an algorithm based on the design of multichannel parallelism and single instruction multiple data on an FPGA, the readout electronics achieve a readout latency of 40 ns from the last sample input to the readout valid output. The feedback data link for cross-instrument communication shows a communication latency of 48 ns when 16 bits of data are transmitted over a 2 m-length cable using a homologous clock to drive the transceiver. With codeword-based triggering mechanisms, readout electronics can be used in dynamic superconducting quantum computing.

Fundamental thresholds of realistic quantum error correction circuits from classical spin models

Mapping the decoding of quantum error correcting (QEC) codes to classical disordered statistical mechanics models allows one to determine critical error thresholds of QEC codes under phenomenological noise models. Here, we extend this mapping to admit realistic, multi-parameter noise models of faulty QEC circuits, derive the associated strongly correlated classical spin models, and illustrate this approach for a quantum repetition code with faulty stabilizer readout circuits. We use Monte-Carlo simulations to study the resulting phase diagram and benchmark our results against a minimum-weight perfect matching decoder. The presented method provides an avenue to assess fundamental thresholds of QEC circuits, independent of specific decoding strategies, and can thereby help guiding the development of near-term QEC hardware.

Fault-tolerant quantum error correction on near-term quantum processors using flag and bridge qubits

Fault-tolerant (FT) computation by using quantum error correction (QEC) is essential for realizing large-scale quantum algorithms. Devices are expected to have enough qubits to demonstrate aspects of fault tolerance in the near future. However, these near-term quantum processors will only contain a small amount of noisy qubits and allow limited qubit connectivity. Fault-tolerant schemes that not only have low qubit overhead but also comply with geometrical interaction constraints are therefore necessary. In this work, we combine flag fault tolerance with quantum circuit mapping, to enable an efficient flag-bridge approach to implement FT QEC on near-term devices. We further show an example of performing the Steane code error correction on two current superconducting processors and numerically analyze their performance with circuit level noise. The simulation results show that the QEC circuits that measure more stabilisers in parallel have lower logical error rates. We also observe that the Steane code can outperform the distance-3 surface code using flag-bridge error correction. In addition, we foresee potential applications of the flag-bridge approach such as FT computation using lattice surgery and code deformation techniques.

Quantum error-correction failure distributions: Comparison of coherent and stochastic error models

We compare failure distributions of quantum error correction circuits for stochastic errors and coherent errors. We utilize a fully coherent simulation of a fault tolerant quantum error correcting circuit for a $d=3$ Steane and surface code. We find that the output distributions are markedly different for the two error models, showing that no simple mapping between the two error models exists. Coherent errors create very broad and heavy-tailed failure distributions. This suggests that they are susceptible to outlier events and that mean statistics, such as pseudo-threshold estimates, may not provide the key figure of merit. This provides further statistical insight into why coherent errors can be so harmful for quantum error correction. These output probability distributions may also provide a useful metric that can be utilized when optimizing quantum error correcting codes and decoding procedures for purely coherent errors.

Comparison of ancilla preparation and measurement procedures for the Steane [[7,1,3]] code on a model ion-trap quantum computer

We schedule the Steane [[7,1,3]] error correction on a model ion trap architecture with ballistic transport. We compare the level one error rates for syndrome extraction using the Shor method of ancilla prepared in verified cat states to the DiVincenzo-Aliferis method without verification. The study examines how the quantum error correction circuit latency and error vary with the number of available ancilla and the choice of protocol for ancilla preparation and measurement. We find that with few exceptions the DiVincenzo-Aliferis method without cat state verification outperforms the standard Shor method. We also find that additional ancilla always reduces the latency but does not significantly change the error due to the high memory fidelity.

A quantum error-correction circuit based on cyclic code

In this paper, the cyclic code of the classic circuit is transformed and transplanted; then, the quantum encoding scheme based on cyclic code and quantum error-correction circuit is constructed. The proposed circuit can correct one-bit error, and the use of redundant bits to encode more than one-bit quantum information breaks the previous limitations of many bits encoding a quantum bit. Compared with the existing coding circuits (Shor code, Steane code and five stable subcode), it shows obvious superiority in the quantum coding efficiency and transmission efficiency.

Physical optimization of quantum error correction circuits with spatially separated quantum dot spins

We propose an efficient protocol for optimizing the physical implementation of three-qubit quantum error correction with spatially separated quantum dot spins via virtual-photon-induced process. In the protocol, each quantum dot is trapped in an individual cavity and each two cavities are connected by an optical fiber. We propose the optimal quantum circuits and describe the physical implementation for correcting both the bit flip and phase flip errors by applying a series of one-bit unitary rotation gates and two-bit quantum iSWAP gates that are produced by the long-range interaction between two distributed quantum dot spins mediated by the vacuum fields of the fiber and cavity. The protocol opens promising perspectives for long distance quantum communication and distributed quantum computation networks.

Approximation of realistic errors by Clifford channels and Pauli measurements

The Gottesman-Knill theorem allows for the efficient simulation of stabilizer-based quantum error-correction circuits. Errors in these circuits are commonly modeled as depolarizing channels by using Monte Carlo methods to insert Pauli gates randomly throughout the circuit. Although convenient, these channels are poor approximations of common, realistic channels such as amplitude damping. Here we analyze a larger set of efficiently simulable error channels by allowing the random insertion of any one-qubit gate or measurement that can be efficiently simulated within the stabilizer formalism. Our error channels are shown to be a viable method for accurately approximating realistic error channels.

Implications of electronics constraints for solid-state quantum error correction and quantum circuit failure probability

In this paper we present the impact of classical electronics constraints on a solid-state quantum dot logical qubit architecture. Constraints due to routing density, bandwidth allocation, signal timing and thermally aware placement of classical supporting electronics significantly affect the quantum error correction circuit's error rate (by a factor of ∼3–4 in our specific analysis). We analyze one level of a quantum error correction circuit using nine data qubits in a Bacon–Shor code configured as a quantum memory. A hypothetical silicon double quantum dot quantum bit (qubit) is used as the fundamental element. A pessimistic estimate of the error probability of the quantum circuit is calculated using the total number of gates and idle time using a provably optimal schedule for the circuit operations obtained with an integer program methodology. The micro-architecture analysis provides insight about the different ways the electronics impact the circuit performance (e.g. extra idle time in the schedule), which can significantly limit the ultimate performance of any quantum circuit and therefore is a critical foundation for any future larger scale architecture analysis.

Toward a scalable, silicon-based quantum computing architecture

Advances in quantum devices have brought scalable quantum computation closer to reality. We focus on the system-level issues of how quantum devices can be brought together to form a scalable architecture. In particular, we examine promising silicon-based proposals. We discover that communication of quantum data is a critical resource in such proposals. We find that traditional techniques using quantum SWAP gates are exponentially expensive as distances increase and propose quantum teleportation as a means to communicate data over longer distances on a chip. Furthermore, we find that realistic quantum error-correction circuits use a recursive structure that benefits from using teleportation for long-distance communication. We identify a set of important architectural building blocks necessary for constructing scalable communication and computation. Finally, we explore an actual layout scheme for recursive error correction, and demonstrate the exponential growth in communication costs with levels of recursion, and that teleportation limits those costs.