Quantum-dot Cellular Automata Full Adder Research Articles

Efficient co-planar adder designs in quantum dot cellular automata: Energy and cost optimization with crossover elimination

Quantum dot cellular automata (QCA) stands as a highly promising nanotechnology, capable of outperforming conventional CMOS technology. Leveraging its advantages, this paper addresses the challenges in adder circuits related to size, delay, and cost by integrating QCA technology. A novel layout for a co-planar full adder in QCA is introduced, featuring a half-adder design with 23 cells in a single layer without any crossover, achieving a delay of 0.25 clock cycles. By utilizing inter-cellular effects inherent in QCA technology, the presented designs offer significant improvements in a variety of design metrics, and a cost efficiency of 64.3%, distinguishing them from traditional logic design approaches. Additionally, in order to ensure an efficient routing channel and a consistent structure of the adder design, a Universal, Scalable, and Efficient (USE) clocking scheme has also been employed. The adder design is further used to build 4-bit and 8-bit Ripple Carry Adders. An extensive study on energy dissipation using QCADesigner-E and QCAPro tools is conducted for three tunneling energies (0.5 Ek, 1 Ek, and 1.5 Ek). The full adder design showcases substantial improvement in energy to delay cost when compared to the closest reported design, achieving improvements of 91.66%, 89.03%, and 88% at 0.5 Ek, 1 Ek, and 1.5 Ek, respectively. The results highlight enhanced circuit efficiency and streamlined layouts, outperforming existing models and offering substantial benefits to high-performance and energy-efficient computing systems.

Quantum‐dot cellular automata based design for overflow detection in two's complement arithmetic operation

AbstractThis article describes designing a low‐power novel circuit for overflow detection in two's complement arithmetic operations. The quantum‐dot cellular automata (QCA) is employed to achieve the nanoscale design. For designing the circuit of the proposed arithmetic overflow detector, a new layout of the QCA full adder is utilized. Two different designs of arithmetic overflow detectors are outlined in this article. The designs are compared based on latency, cell count, and device area. Based on the comparison, the best design for an arithmetic overflow detector is presented. The circuit cost for all the designs is also shown in this work. Besides, thermal power's effect on the output cell's polarization has also been investigated. The power dissipation of all proposed QCA layouts is estimated.

Four-bit Nanoadder Controlled by Five-Inputs Majority Elements

This paper presents a nano circuit of a full one-bit adder on the proposed five-input majority element. This innovative full adder design is used to development of a four-bit adder based on it. We offer a new single-bit full adder and a four-bit adder nano circuit in quantum-dot cellular automata technology. The proposed design four-bit adder utilizes only 231 quantum cells in a 0.49 µm2 area. It has a reduction in the number of cells, delay and energy dissipation at 1 K compared to the existing works. The QCADdesigner version 2.0.3 tool implements the developed quantum-dot cellular automata full adder and four-bit adder circuits. The implementation results show that the developed quantum-dot cellular automata full adder and four-bit adder circuits have an improvement over other quantum-dot cellular automata full adder circuits.

A novel efficient coplanar QCA full adder and full subtractor design

ABSTRACT Quantum-dot Cellular Automata (QCA) nanotechnology is an alternative technology with high speed, high density and low power for designing nanoscale circuits. A novel design of Full Adder-Subtractor based on full subtractor using single layer is proposed. The proposed architecture has a major advantage in terms of complexity, area, latency, and power consumption as compared to previous designs. The proposed QCA full subtractor showed higher performance concerning area with a reduction of 66%, and complexity with a reduction of 51% over best existing circuit designs. However, the proposed design of full Adder-Subtractor achieved a reduction of 74% in area, with 70% improvement in complexity, 33% reduction in latency by using two clock phases, and 95% improvement in cost needed over the best reported circuits using single-layer design. Total cell area and cost for the Full Adder-Subtractor were 0.01 μm2 and 0.07, respectively. Results showed that power consumption for the novel design was minimal. Therefore, the suggested Full Adder-Subtractor provides 86% less total energy consumption for 0.5Ek tunnelling energy level. These designs were tested and simulated using the freely known QCA Designer tool version 2.0.3. The energy dissipation result was realised by using the QCAPro energy estimation tool.

An optimized arithmetic logic unit in quantum-dot cellular automata (QCA) technology

Quantum-dot cellular automata (QCA) are one of the technologies suggested for implementing circuits at a Nanoscale. This technology has features such as low dissipation power, high speed, low occupation area, and high density due to the lack of electric currents in the circuit and the use of Columbus interaction to transmit information. The arithmetic logic unit (ALU) is one of the significant components of digital computing systems that can perform arithmetic and logical operations on binary data. In this paper, an efficient one-bit ALU in QCA is suggested based on a new formulation that can perform eight mathematical operations and four logical operations. Moreover, we have suggested a novel QCA full-adder and an effective 4:1 QCA multiplexer that have been used in the suggested QCA ALU. The simulation results using QCADesigner2.0.3 software showed that the suggested circuits work well.

QCA with reversible arithmetic and logic unit for nanoelectronics applications

PurposeIn this research work, brief quantum-dot cellular automata (QCA) concepts are discussed through arithmetic and logic units. This work is most useful for nanoelectronic applications, VLSI industry mainly depends on this type of fault-tolerant QCA based arithmetic logic unit (ALU) design. The ALU design is mainly depending on set instructions and rules; these are maintained through low-power ultra-functional tricks only possible with QCA-based reversible arithmetic and logic unit for nanoelectronics. The main objective of this investigation is to design an ultra-low power and ultra-high-speed ALU design with QCA technology. The following QCA method has been implemented through reversible logic.Design/methodology/approachQCA logic is the main and critical condition for realizing NANO-scale design that delivers considerably fast integrate module, effective performable computation and is less energy efficiency at the nano-scale (QCA). Processors need an ALU in order to process and calculate data. Fault-resistant ALU in QCA technology utilizing reverse logic is the primary objective of this study. There are now two sections, i.e. reversible ALU (RAU), logical (LAU) and arithmetical (RAU).FindingsA reversible 2 × 1 multiplexer based on the Fredkin gate (FRG) was developed to allow users to choose between arithmetic and logical operations. QCA full adders are also implemented to improve arithmetic operations' performance. The ALU is built using reversible logic gates that are fault-tolerant.Originality/valueIn contrast to earlier research, the suggested reversible multilayered ALU with reversible QCA operation is imported. The 8- and 16-bit ALU, as well as logical unit functioning, is designed through fewer gates, constant inputs and outputs. This implementation is designed on the Mentor Graphics QCA tool and verifies all functionalities.

CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability

The significant physical challenges of Complementary Metal Oxide Semiconductor (CMOS) technology drives it on the brink of ultimate limit. With the surfacing of tremendous research findings, Quantum dot cellular automata (QCA) has emerged as a new technology in nanoscale era as a viable alternative to CMOS technology. Besides its wide acceptance, QCA-based nanoscale circuits are highly susceptible to huge fault/error rates. Thus, the fault tolerance and testability have become the utmost necessity for ensuring reliable QCA circuit. Toward this direction, conservative logic plays a vital role to achieve such reliability. In this paper, a Conservative Full Adder (CFA) is proposed with a simplified testable logic to detect the internal fault in the circuit. A simple majority–minority-based testing logic in the circuit is augmented for the detection of conservative (bit preserving) nature. Besides the testable feature, the full adder is chosen for its versatility in Arithmetic and Logic Unit (ALU) synthesis. Experimental result establishes the superiority of the proposed logic in terms of design capability as well as testability. Also, a comprehensive analysis of energy dissipation is performed to ensure the robustness of the proposed testable conservative adder. The QCA layout design and functional verification of the design are performed using the QCADesigner tool and Hardware Description Language for QCA (HDLQ) tool, respectively. The QCAPro simulator is used to evaluate the energy dissipation of the circuit.

An Efficient Quantum-Dot Cellular Automata Full Adder Based on a New Convertible 7-Input Majority-Not Gate

Quantum-dot cellular automata (QCA) is one of the most promising emerging paradigms offered for substitution of ongoing MOSFET technology. In order to qualify the QCA technology, all the previously designed circuits, either combinational or sequential, have been redesigned using QCA cell interaction. In this way, adder circuits, which play the most significant role in the arithmetic structures, have been extensively explored. In this paper, in the first step, a new single-layer 7-input majority-not gate is presented. This gate can be easily converted to a 5- or 7-input majority gate to form diverse QCA circuits. The extensive energy dissipation and structural evaluations over the proposed 5-input majority gate and the best previously published ones prove its prominent performance. In the next step, this well-shaped gate is leveraged as a basilar structure for implementation of an ultra-high speed QCA full adder. With respect to the counterpart designs, our proposed one surpasses all the previously published full adders in different points of views such as computation speed and number of consumed cells. QCADesigner and QCAPro tools are used as popular simulation engines to authenticate the circuit functioning and to measure energy dissipation, respectively.

A novel fast and small XOR-base full-adder in quantum-dot cellular automata

Among cutting-edge nanotechnologies, quantum-dot cellular automata (QCA) is a well-matched substitute for transistor-based technologies. Full-adder as a primary element of computational circuits has a great effect on other circuits. Hence this paper presents a new schematic design of QCA full-adder (QFA) to implement an efficient layout with minimum cells. The simple structure of the proposed design in minimum latency makes the aforementioned layout unique among state-of-the-art QFAs. Besides, different sizes of ripple carry adder (RCA) are implemented using this efficient full-adder layout to show its applicability. The proposed design of this work are simulated using QCADesigner tool. Moreover, The proposed full-adder have verified with physical formulas. 32.43% decreasing cell count and 50% increasing speed is the result of a comparison between our optimum QFA layout and previously published design with a similar structure. Ultimately different sizes of ripple carry adders of this paper are compared to the previous layouts and results show the performance of suggested RCA’s structure.

Utilizing charge reconfigurations of quantum-dot cells in building blocks to design nanoelectronic adder circuits

In the quantum-dot cellular automata (QCA) nanotechnology, the cell-based building block can be designed by utilizing the charge reconfiguration of quantum-dot cells in order to achieve the desired function with optimal implementation. In this paper, new advanced nanostructures based on quantum-dot cells are introduced to three-input XOR gate and two-to-one multiplexer, which can be considered in addition to the conventional majority voter as basic building blocks used in implementing well-optimized QCA circuits. Consequently, these blocks are used in this paper to implement new single-layer QCA full-adders and four-bit adders as motivational applications. Moreover, an innovative design approach of full-adder is proposed to avoid the presence of inputs surrounded by QCA cells and to prevent the use of crossovers when building multi-bit adders. The proposed QCA layouts are simulated and evaluated as results indicate that proposed designs are superior to the previous designs in the literature.

The design and implementation of a robust single-layer QCA ALU using a novel fault-tolerant three-input majority gate

Inverter and majority gates are considered as two important primitive gates for designing logical circuits in the quantum-dot cellular automata (QCA) technology. Up to now, many QCA layouts have been introduced for three-input majority gates, most of which are not robust against the QCA defects and so they are prone to faults. In this paper, we propose an efficient fault-tolerant 3-input majority gate with ten simple and rotated cells whose output signal strength is very high (± 9.93e−001). The fault tolerance of the proposed structure is investigated against cell omission, extra-cell deposition, and displacement defects. The results show that the proposed structure is 100% and 90% tolerant against single-cell omission and extra-cell deposition defects. Moreover, the error probability of the proposed gate under cell omission and extra-cell deposition defects is investigated through analytical modeling. Using the proposed fault-tolerant structure, two basic circuits including a fault-tolerant QCA full-adder and a fault-tolerant 2:1 QCA multiplexer are introduced. Finally, using the proposed circuits, a fault-tolerant one-bit arithmetic logic unit with four mathematical and logical operations is designed and implemented. To verify the proposed three-input majority gate, some physical proofs are provided. The results of simulations by QCADesigner 2.0.3 show that the proposed circuits work well. The power analysis of the proposed structure is performed using a QCAPro tool. The comparison results show that the proposed circuits are much better than the previous designs.

Effective RCA design using quantum dot cellular automata

Quantum dot Cellular Automata (QCA) is a transistor less technology alternative to CMOS for developing low-power, high speed digital circuits. Adder circuits are broadly employed in all digital computation systems. In this paper, a novel coplanar QCA full adder circuit is proposed which is designed with minimum number of QCA cells. The proposed full adder requires only 13 QCA cells, an area of 0.008 μm2 and delay of about 2 clock cycles to implement its function. Then an efficient 4-bit Ripple Carry Adder (RCA) is designed based on the proposed full adder that performs higher end addition in an effective way. Simulations results are obtained precisely using QCA designer tool version 2.0.3. Also the simulation results shows that the proposed 4-bit Ripple Carry Adder (RCA) requires only 70 QCA cells, an area of 0.18 μm2 and delay of about 5 clock cycles to implement its function with enhanced performance in terms of latency, area and QCA Cost. From the comparisons, it is found that our work achieves over 55% improvement in QCA cell count.

Design of high-performance QCA incrementer/decrementer circuit based on adder/subtractor methodology

This paper focuses on a novel design of an adder/subtractor-based incrementer/decrementer using quantum-dot cellular automata (QCA) technology. QCA is a promising nanotechnology that offers new techniques of computation and data transmission. We use the multilayer crossover technique in the proposed designs to achieve low latency and area for the scalability feature. Moreover, new designs of QCA half and full adders are proposed to improve the operating speed of the incrementer/decrementer. The working of the proposed designs is analyzed via the QCA simulator tool, and the results are compared with previous studies in terms of cell count, area, and latency. According to the analysis, the presented designs perform well; for example, the proposed 4-bit incrementer design shows an improvement of 65 % in terms of area usage and 3.2 times lower latency compared to its existing counterpart.

Design of Ultra-Efficient Reversible Gate Based 1-bit Full Adder in QCA with Power Dissipation Analysis

The difficulties which the CMOS technology is facing at the nano scale has led to the investigation of quantum-dot cellular automata (QCA) nanotechnology and reversible logic as an alternative to conventional CMOS technology. In this paper, these two paradigms have been combined. Firstly, a new 3 × 3 reversible gate, SSG-QCA, which is universal and multifunctional in nature, is proposed and implemented in QCA using conventional 3-input majority voter based logic. By using the concept of explicit interaction of cells, the proposed gate is further optimized and then used to design an ultra-efficient 1-bit full adder in QCA. The universal nature has been verified by designing all the logic gates from the proposed SSG-QCA gate whereas the multifunctional nature is verified by implementing all the 13 standard Boolean functions. The proposed 3 × 3 gate and adder designs are then extensively compared with the existing literature and it is observed that the proposed designs are ultra-efficient in terms of both area and cost in QCA technology. In addition to this energy dissipation analysis for different scenarios is also done on all the designs and it is observed that the proposed designs dissipate minimum energy thereby making them suitable for ultra-low power designs.

Design of an Efficient Multilayer Arithmetic Logic Unit in Quantum-Dot Cellular Automata (QCA)

Quantum-dot cellular automata (QCA) is a new nano-scale technology that due to making significant improvements in the design of electronic circuits can be considered as an appropriate alternative to CMOS technology. The arithmetic logic unit (ALU) is a fundamental component of the central processing unit to carry out the arithmetic and logical operations that multiplexer and full adder play an important role in its operations. In this brief, based on the extracted features of the arithmetic operations of the ALU, we propose a new special low-complexity QCA 4:1 multiplexer, which is application-specific to the proposed ALU. Moreover, a new QCA full adder is proposed based on the cell interaction. Likewise, a QCA multilayer ALU structure is designed based on the validated proposed structures to carry out four logical and eight arithmetic operations. The functional correctness of the proposed structures are evaluated by QCADesigner tool; also, QCAPro as an accurate power estimator tool is applied to investigate their power dissipation. The simulation results demonstrate that the proposed structures outperform in comparison to counterpart designs in terms of cell number, area, latency, and power consumption.

Performance evaluation of an ultra-high speed adder based on quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is among the most promising nanotechnologies as the substitution for the current metal oxide semiconductor field effect transistor based devices. Therefore, lots of attention have been paid to different aspects to improve the efficiency of QCA circuits. In this way, the adder circuits are widely investigated since their performance can directly affect the whole digital system performance. In this paper, a new ultra-high speed QCA full adder cell is proposed based on multi-layer structures. The proposed full adder cell is simple in design using 3-input Exclusive-OR (TIEO), which computes the Sum bits and Majority gate, which computes the Carry bits. To verify the efficacy of the presented full adder cell, it is considered, the main constructing block in 4-bit ripple carry adder circuit. Hence, significant improvements in terms of area and cell count have been achieved. Particularly simulation results show 20% and 1.8% reduction respectively in the area and cell count overhead. Detailed performance evaluation and structural analysis are performed in different aspects to authenticate the proposed circuits (one-bit and 4-bit) having superb performance in comparison to previously reported works. QCADesigner CAD tool has been used to verify the correct functionality of the proposed architectures.

Carry save adder and carry look ahead adder using inverter chain based coplanar QCA full adder for low energy dissipation

Quantum-dot cellular automata (QCA) technology offers the potential option for performing transistor-less calculations at the nanoscale. In this paper, we introduce a new full adder structure using an inverter chain on a single layer. By utilizing the proposed full adder structure, we design and implement a carry save adder and carry look-ahead adder. Some of these techniques like pipeline structures or asynchronous timing becoming more attractive and are gaining more attention than other solutions. This paper mainly focuses on the high circuit density and energy-efficient aspects of QCA circuits. The design exploits the inherent pipeline nature of QCA, which can lead to an enormous reduction in area using an inverter chain since all computations can be computed in a single block. A comparison among our results and typical structures shows that the presented structures outperformed the best existing designs with respect to area, latency, and cell count. Our structures are more suitable elements for realizing complex QCA circuits with very high operating speed. Functional verification and energy consumption analyses were conducted by well known tools.

Novel single layer fault tolerance RCA construction for QCA technology

Quantum-dot Cellular Automata (QCA) technology has become a promising and accessible candidate that can be used for digital circuits implementation at Nanoscale, but the circuit design in the QCA technology has been limited due to fabrication high-defect rate. So, this issue is an interesting research topic in the QCA circuits design. In this study, a novel 3-input Fault Tolerance (FT) Majority Gate (MG) is developed. Accordingly, an efficient 1-bit QCA full adder is developed using the developed 3-input MG. Then, a new 4-bit FT QCA Ripple Carry Adder (RCA) is developed based on the proposed 1-bit FT QCA FA. The developed circuits are implemented in the QCA Designer tool version 2.0.3. The results indicate that the developed QCA circuits provide advantages compared to other QCA circuits in terms of double and single cell missing defect, area and delay time.

Robust Coplanar Full Adder Based on Novel Inverter in Quantum Cellular Automata

Quantum dot cellular automata (QCA) is one of the nano-scale computing paradigms which promises high speed and ultra-low power consumption. Since the one-bit full adder is a fundamental building block of arithmetic circuits, designing an efficient QCA full adder cell is very imperative in this new technology. In this paper, we propose a QCA full adder using a new inverter gate which leads to reduced complexity and area occupation. The proposed layout is simulated by the QCA designer engines. We also provide a performance comparison of our proposed QCA full adder with the previous relevant designs. Furthermore, a detailed analysis of energy dissipation is performed which demonstrates the superiority of the proposed design in terms of the energy efficiency.

A Novel Full Adder/Subtractor in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA), one of the alternative CMOS technologies at a nano scale, promises to design digital circuits with extra low-power, extremely dense and high speed structures. In this paper, a new QCA gate with three inputs and two outputs is first introduced; this operates on the basis of cell interactions. Then, low complexity and high-speed QCA full-adder and full-subtractor structures are proposed by applying different formulations, which are based on the introduced gate. Finally, a novel QCA full adder/subtractor is presented with the synergy of the proposed QCA full-adder and full-subtractor structures as well as a proposed optimal single layer 2:1 QCA multiplexer. The proposed designs are simulated using the QCA Designer 2.0.3. The simulation results confirm that the proposed circuits work well. A comparative analysis indicates the superiority of the proposed designs compared to the other related designs. Moreover, the QCAPro power estimator tool is utilized to evaluate the power dissipation of the proposed designs.