A novel architecture to implement quadrature voltage-controlled oscillators (QVCOs), based on the coupled phase-locked loop (CPLL) technique, is presented. The proposed solution allows to overcome the trade-off between low phase noise and small quadrature error, typical of conventional QVCOs. Both figure-of-merit (FoM) can then be optimized simultaneously. Within the CPLL bandwidth, the QVCO phase noise is even improved by 3 dB with respect to the phase noise of the standalone free-running oscillators in the loop. Prototypes realized in a 28 nm bulk CMOS technology operate from 24 to 29.2 GHz (a 20% tuning range) and show a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-134$</tex-math> </inline-formula> dBc/Hz phase noise at 10 MHz offset from the 24 GHz carrier. The measured average quadrature error across the tuning range is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.9^\circ$</tex-math> </inline-formula> . The QVCO dissipates 60 mW; its FoM is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-184$</tex-math> </inline-formula> dBc/Hz. The QVCO core area amounts to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.2$</tex-math> </inline-formula> mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> .