Quadrature Oscillator Research Articles

Analysis of Self-Injection-Coupled Quadrature Oscillator: Oscillation Amplitude and Phase Error

Analysis of Self-Injection-Coupled Quadrature Oscillator: Oscillation Amplitude and Phase Error

Design and Implementation of CNFET-based Universal Bi-Quad Filter and Quadrature Oscillator Utilizing Innovative Floating Current Source (IFCS)

Design and Implementation of CNFET-based Universal Bi-Quad Filter and Quadrature Oscillator Utilizing Innovative Floating Current Source (IFCS)

A low-power quadrature voltage-controlled oscillators with LC emitter degeneration phase shift technique

This paper introduces a novel phase-shifting technique for quadrature voltage-controlled oscillators (QVCOs) utilizing an LC emitter degeneration architecture. The proposed technique enables a phase shift of up to ±90°in the transconductance of the coupling path while also generating a negative input resistance. This innovative approach avoids phase ambiguity, mitigates the trade-off between phase noise and phase error, and substantially reduces QVCO power consumption. Moreover, compared to conventional capacitance emitter degeneration methods, the LC emitter degeneration structure has a lower equivalent input capacitance, expanding the QVCO’s frequency tuning range. The designed QVCO is implemented using a 180 nm SiGe BiCMOS technology, occupying a compact area of 0.037 mm2. Post-layout simulation evaluations under various process, voltage, and temperature (PVT) conditions validate the robustness and reliability of the design. Results indicate a phase noise of 102.7 dBc/Hz at a 1 MHz offset from a 22.1 GHz carrier, a frequency tuning range of 25.2%, a phase error of 0.9°, and a power consumption of 12 mW from a 1.1 V supply, achieving a figure of merit (FoM) of 178.8 dBc/Hz.

Analysis of voltage mode quadrature oscillator based on fin field-effect transistor

This study introduces a new voltage mode sinusoidal quadrature oscillator (V-M.S.Q.O.) that employs multioutput Z copy voltage differencing transconductance amplifiers (M-Zc-VDTA) as an active filter based on FinFET transistor. The suggested circuits have low passive and active sensitivities, and they may be constructed as integrated circuits using only two M-Zc-VDTAs and three grounded capacitors. The circuits produce two (VM) sinusoidal quadrature oscillator voltage results by adjusting the electronic base current and frequency of the oscillation condition separately. FinFET technology lowers power consumption while improving circuit performance. They can also produce amplitude shift keying-amplitude modulation signals for communication electronics systems and provide electrical basis control of output current amplitude. Using the Cadence Virtuoso tool with a 7 nm parameter, simulation results were obtained for the suggested circuits.

A Quadrature Oscillator with a Frequency-Tuned Distributed RC Network Analysis

This paper introduces an innovative two-stage distributed RC oscillator design, enhancing the noise performance and frequency stability for compact electronic devices. This work significantly reduces the comparator noise and improves system reliability by implementing a novel approach to increase the signal transition slope, coupled with optimized resistor and capacitor configurations. The study employs a quadrature oscillator topology and a precise reference voltage generation method, effectively addressing the challenges of mismatch and noise performance. A 469.2 kHz quadrature oscillator with two-stage distributed RC is implemented with a 0.18 μm CMOS process, achieving a FoM of −160 dBc/Hz at 100 Hz with a stable −20 dB roll-off in the phase noise and an Allan deviation floor of less than 0.7 ppm.

A posteriori error estimates for the Richards equation

The Richards equation is commonly used to model the flow of water and air through soil, and it serves as a gateway equation for multiphase flows through porous media. It is a nonlinear advection–reaction–diffusion equation that exhibits both parabolic–hyperbolic and parabolic–elliptic kind of degeneracies. In this study, we provide reliable, fully computable, and locally space–time efficient a posteriori error bounds for numerical approximations of the fully degenerate Richards equation. For showing global reliability, a nonlocal-in-time error estimate is derived individually for the time-integrated H 1 ( H − 1 ) H^1(H^{-1}) , L 2 ( L 2 ) L^2(L^2) , and the L 2 ( H 1 ) L^2(H^1) errors. A maximum principle and a degeneracy estimator are employed for the last one. Global and local space–time efficiency error bounds are then obtained in a standard H 1 ( H − 1 ) ∩ L 2 ( H 1 ) H^1(H^{-1})\cap L^2(H^1) norm. The reliability and efficiency norms employed coincide when there is no nonlinearity. Moreover, error contributors such as space discretization, time discretization, quadrature, linearization, and data oscillation are identified and separated. The estimates are also valid in a setting where iterative linearization with inexact solvers is considered. Numerical tests are conducted for nondegenerate and degenerate cases having exact solutions, as well as for a realistic case and a benchmark case. It is shown that the estimators correctly identify the errors up to a factor of the order of unity.

Area-Efficient and Wideband Tunable Quadrature Colpitts Oscillator with Active Inductors

This study presents a new wide-tunable, area-efficient and low-phase noise quadrature voltage-controlled oscillator(QVCO). Initially, a modified Colpitts voltage-controlled oscillator (VCO) is proposed in which all transistors are cross-connected in a self-biased scheme to increase negative resistance and facilitate the startup condition. Besides, instead of a passive inductor, a modified tunable active inducer (AI) is used in the proposed Colpitts VCO. Then a new AI-based QVCO is presented by the in-phase anti-phase coupling of two identical Colpitts VCOs. The core VCOs are coupled by the current source transistors of the AI and in this way, no extra coupling devices are used. The proposed AI-based QVCO is designed and simulated in TSMC [Formula: see text] CMOS technology by Cadence. Post-layout simulation results show that the proposed QVCO occupies only [Formula: see text] of chip area, and has a phase noise of −106.6[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset from the 0.7[Formula: see text]GHz oscillation frequency. A wide frequency tuning range (FTR) of 68% (i.e., 0.68–1.4[Formula: see text]GHz) is achieved by adjusting the tuning voltage of the active inductor (AI), and the total power consumption is 7.2[Formula: see text]mW. Coarse and fine frequency tuning of the QVCO is available by changing the emulated inductors and varactors, respectively, that gives [Formula: see text] of 1100 and 34[Formula: see text]MHz/V, respectively.

Influence of quadrature transformation imbalance on the noise immunity of signal reception with amplitude-phase shift keying

Objectives. At the present time, amplitude-phase shift keyed (APSK) signals are actively used in satellite communication systems. In particular, they are applied in systems which operate in a limited radio frequency spectrum with increased data transmission quality requirements. Such systems use multi-channel type receivers with maximum likelihood decision on the received symbol (correlation receiver) or quadrature type receivers. The noise immunity of these receivers is directly dependent on the quality of the formation of reference oscillations. These oscillations are reference signals for correlation receivers and in-phase and quadrature components for quadrature receivers. The aim of the work is to analyze the influence of the amplitude and phase parameter spread of the in-phase and quadrature channels on the noise immunity of receiving APSK signals with a circular shape of the signal constellation.Methods. Methods of statistical radio engineering, theory of optimal signal reception, and computer simulation are used.Results. The study established the characteristics of noise immunity of the APSK signal reception depending on the spread of parameters of the quadrature converter. The theoretical calculations were confirmed by the results of modeling the transmission of APSK signals in a Gaussian communication channel. A comparison with systems using quadrature amplitude modulation (QAM) was carried out, in order to assess system stability in the presence of spread parameters among other similar systems.Conclusions. The studies enabled us to conclude that an imbalance of the quadrature reference oscillations can lead to a significant decrease in the noise immunity of radio systems using APSK signals. The minimum energy loss due to imbalance of quadrature reference oscillations is achieved when the imbalance value is less than 10% in amplitude and 2°–3° in phase. The amplitude imbalance of quadrature reference oscillations when receiving QAM signals is more pronounced than in the case of APSK signals. The phase imbalance affects approximately the same.

Bulk Cum QFG-Driven FVF Double Recycling Current Mirror Subthreshold OTA Based CCII+ Cell and Applications

This paper presents a low-voltage low-power second generation CCII+ cell using bulk-driven FVF class AB mode operated double recycling current mirror OTA. The OTA is used in the input core of CCII+ cell utilizes bulkcum Quasi Floating Gate (QFG)-based voltage to current converter and Partial Positive Feedback (PPF) to enhance the performance of the circuit. The circuit permits closely railto- rail input common mode range, high output current drive capability with low dual power supply of ± 0.25 V. This circuit produces low input referred noise of 1.65 μV/sqrt Hz, dissipates ultra-low power of 342 nW and is suitable for lowfrequency applications, such as bio-signal processing. Further, to validate this design, a MISO type voltage mode biquadratic filter and voltage mode two phase quadrature oscillator are currently being implemented using this CCII+ cells. The circuit is simulated in tanner EDA tools using 180 nm n-tub CMOS process technology with low bias current of 18 nA.

Correction: Low-Frequency Resistorless Electronically Tunable Quadrature Oscillator Based on an EX-CCCII

Correction: Low-Frequency Resistorless Electronically Tunable Quadrature Oscillator Based on an EX-CCCII

General closed‐form equations for amplitude of parallel coupled quadrature oscillator

SummaryIn this paper, for the first time, a new method with closed‐form analytical equations is presented to calculate the oscillation amplitude of fourth‐order oscillators, such as quadrature oscillators. This method is actually based on the general form of the differential equations describing the structure of the fourth‐order oscillators and finding a solution for the nonlinear differential equations governing this type of oscillator. The introduced method is a general method that is valid for all fourth‐order oscillators and is also independent of the oscillation frequency. Using the proposed method, complex and time‐consuming simulation tools will no longer be needed to calculate the oscillation amplitude in a steady state. Moreover, the presented closed‐form equations help the designers to understand the design compromises and design the oscillator for their specific and desired conditions. In addition, to evaluate the correctness of the presented equations, a comprehensive analysis of the oscillation amplitude of the quadrature oscillator in the steady state is performed, and a closed‐form equation is presented for the oscillation amplitude of the oscillator in the steady state, which is proposed for the first time in this paper. A comparison between the simulation results and theoretical computations confirms the validity of the proposed method.

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm2. The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research.

A miniature tunable quadrature shadow oscillator with orthogonal control

This article presents a new design of a quadrature shadow oscillator. The oscillator is realized using one input and two outputs of a second-order filter cell together with external amplifiers in a feedback configuration. The oscillation characteristics are controlled via the external gain without disturbing the internal filter cell, following the concept of the shadow oscillator. The proposed circuit configuration is simple with a small component-count. It consists of, two voltage-different transconductance amplifiers (VDTAs) along with a couple of passive elements. The frequency of oscillation (FO) and the condition of oscillation (CO) are controlled orthogonally via the dc bias current and external gain. Moreover, with the addition of the external gain, the frequency range of oscillation can be further extended. The proposed work is verified by computer simulation with the use of 180 nm complementary metal–oxide–semiconductor (CMOS) model parameters. The simulation gives satisfactory results of two sinusoidal output signals in quadrature with some small total harmonic distortions (THD). In addition, a circuit experiment is performed using the commercial operational transconductance amplifiers LM13700 as the active components. The circuit experiment also demonstrates satisfactory outcome which confirms the validity of the proposed circuit.

Amplitude Control Loop to Compensate for I/Q Mismatch in an Accurate Quadrature LC Oscillator

In this paper, a novel parallel-coupled quadrature LC oscillator (PC-QO) is presented that can automatically eliminate imbalances of output phase and amplitude resulting from mismatches in the LC tanks. The method of using unequal coupling factors in a parallel-coupled quadrature oscillator is the base of this design; canceling the phase and amplitude errors takes place by tuning the imbalanced coupling factor using tuneable tail currents. First, the proposed circuit senses the amplitude error and then adjusts the coupling factors according to the situation. We show that using the inversely proportional coupling factors can eliminate the phase and amplitude error simultaneously. In other words, this design uses the amplitude control loop to cancel the phase and amplitude error. The circuit has been simulated using TSMC 0.18 CMOS practical model to confirm the high accuracy of the analysis and capability of the canceling [Formula: see text]/[Formula: see text] mismatch technique. The simulation results show that the phase noise of the proposed quadrature voltage controlled oscillator (QVCO) is −123.9 dBc/Hz at 1[Formula: see text]MHz offset from 4.4[Formula: see text]GHz operation frequency. The total power consumption of the QVCO is 3.4[Formula: see text]mW.

A low phase noise quadrature VCO using super‐harmonic coupling technique in 65‐nm CMOS technology

SummaryThis paper presents a new low phase noise (PN) quadrature voltage controller oscillator (QVCO), which includes four class C LC‐VCOs oscillated at 13 GHz operating frequency with 45‐degree phase differences from each other. By combining the second harmonics (super‐harmonic) of the LC‐VCOs, the quadrature outputs with low PN at 26 GHz are generated. To assess the performance of the proposed QVCO, post‐layout simulations are performed in 65‐nm CMOS technology with a 0.6 V supply voltage. The post‐layout results represent that the proposed circuit has 26 GHz quadrature outputs with the PN of −116.4 at 1 MHz offset frequency. Also, the proposed QVCO occupies an area of 0.366 mm2 and consumes 10.4 mW of power. Therefore, the proposed QVCO is a good candidate for 5G applications.

Gain-Controllable Transadmittance-Mode First-Order Allpass Filters with Electronic Tune Using Single Active Element

First-order allpass filters are analog filters with a unit magnitude response, but they change the phase shift between input and output signals at various frequencies. This paper presents the transadmittance-mode first-order allpass filters based on the modified current-controlled current differencing transconductance amplifier (M-CCCDTA). The proposed filters utilize a single M-CCCDTA and a grounded capacitor with no external resistors, making them well suited for implementation in an integrated circuit. The gain and phase response of the proposed filters can be adjusted electronically and separately. Also, the high output impedance of the proposed filters at both the input voltage node and the output current node makes cascading easy without the need for buffer devices. A quadrature sinusoidal oscillator based on the proposed first-order allpass filter has been designed as an example of an application. The PSpice simulation and actual experiments are utilized to validate the functionality of the proposed filters. The simulation and experimental results are consistent with the idea of anticipation.

A New Electronically Tunable Transimpedance-Mode OTA-Based First-Order Universal Filter and its Quadrature Oscillator Application

This paper suggests a new operational transconductance amplifier (OTA) based electronically tunable transimpedance-mode first-order universal filter (FOUF). The suggested FOUF produces all-pass (AP), high-pass (HP) and low-pass (LP) filter responses simultaneously. It employs three OTAs, two grounded resistors and only one grounded capacitor. Owing to use of grounded passive elements, the suggested FOUF is suitable for integrated circuit implementation. It operates at low power supply voltages. Additionally, the resonance frequency of the suggested AP filter can be adjusted in a wide frequency range. However, the suggested FOUF consists of only one matching condition. Moreover, a sinusoidal quadrature oscillator (QO) application that is derived from the suggested FOUF topology is given. The suggested FOUF and its QO application are simulated by using 0.18-[Formula: see text]m TSMC technology parameters in the SPICE program to validate the presented theory. Finally, an experimental test is performed to demonstrate workability of the suggested AP filter.

Current-Mode First-Order Versatile Filter Using Translinear Current Conveyors with Controlled Current Gain

This paper offers a new current-mode first-order versatile filter employing two translinear current conveyors with controlled current gain and one grounded capacitor. The proposed filter offers the following features: realization of first-order transfer functions of low-pass, high-pass, and all-pass current responses from single topology, availability of non-inverting and inverting transfer functions for all current responses, electronic control of current gain for all current responses, no requirement of component-matching conditions for realizing all current responses, low-input impedance and high-output impedance which are required for current-mode circuits, and electronic control of the pole frequency for all current responses. The proposed first-order versatile filter is used to realize a quadrature sinusoidal oscillator to confirm the advantage of the new topology. To confirm the functionality and workability of new circuits, the proposed circuit and its application are simulated by the SPICE program using transistor model process parameters NR100N (NPN) and PR100N (PNP) of bipolar arrays ALA400-CBIC-R from AT&T.

0.3-V Voltage-Mode Versatile First-Order Analog Filter Using Multiple-Input DDTAs.

This paper presents a versatile first-order analog filter using differential difference transconductance amplifiers (DDTAs). The DDTA employs the bulk-driven (BD) multiple-input MOS transistors technique (MI-MOST) operating in the subthreshold region. This results in low-voltage and low-power operational capability. Therefore, the DDTA, designed using 130 nm CMOS technology from UMC in the Cadence environment, operates with 0.3 V and consumes 357.4 nW. Unlike previous works, the proposed versatile first-order analog filter provides first-order transfer functions of low-pass, high-pass, and all-pass filters within a single topology. The non-inverting, inverting, and voltage gain of the transfer functions are available for all filters. Furthermore, the proposed structure provides high-input and low-output impedance, which is required for voltage-mode circuits. The pole frequency and voltage gain of the filters can be electronically controlled. The total harmonic distortion of the low-pass filter was calculated as -39.97 dB with an applied sine wave input signal of 50 mVpp@ 50 Hz. The proposed filter has been used to realize a quadrature oscillator to confirm the advantages of the new structure.

A 52-to-57 GHz CMOS Phase-Tunable Quadrature VCO Based on a Body Bias Control Technique

This paper presents a 52-to-57 GHz CMOS quadrature voltage-controlled oscillator (QVCO) with a novel I/Q phase tuning technique based on a body bias control method. The QVCO employs an in-phase injection-coupling (IPIC) network comprising four diode-connected FETs for the quadrature phase generation. The I/Q phase error is calibrated by controlling the body bias voltage offset of the QVCO’s four core FETs. This technique effectively covers a wide range of I/Q phase error between −13.4° and +10.7°. It also minimally induces the unwanted variations in the phase noise, current dissipation, and oscillation frequency, which were found to be only 0.4 dB, 0.07%, and 36 MHz, respectively. After the IPIC-QVCO, a phase-tunable two-stage LO buffer employing a 3-bit switched-capacitor bank was added for additional phase tuning, leading to the extension of the phase tuning range up to −22.7–+20.0°. The proposed QVCO is implemented in a 40 nm RF CMOS process. The measured results show that the QVCO covers a frequency band from 52.4 to 57.6 GHz while consuming 26.2 mW. The phase noise and the figure-of-merit of the QVCO are −91.8 dBc/Hz at 1 MHz offset and −172.4 dBc/Hz, respectively. We also realized a fully integrated 55 GHz quadrature RF transmitter employing the phase-tunable QVCO and LO generator. The effectiveness of the proposed phase-tunable LO generator was confirmed by verifying the image rejection ratio (IRR) calibration at the RF output.