Quadrature Direct Digital Frequency Synthesizer Research Articles

VLSI Design and Implementation of Efficient Software Defined Radio Using Optimized Quadrature Direct Digital Frequency Synthesizer on FPGA

Abstract This paper presents an framework for efficient design and implementation of software defined radio (SDR) on FPGA platform using optimized Quadrature Direct Digital Frequency Synthesizer (QDDFS). An basic SDR System consists of RF Antennas, Analog to Digital converter (ADC), Digital to Analog converter (DAC), Filters and processing units. Reconfigurability and optimization can be achieved in the processing unit to a maximum extent. Processing unit of the SDR System is designed and implemented completely in this paper. The important parts of the SDR system designed are 16-Quadrature Amplitude Modulation (16-QAM), Orthogonal Frequency Division Multiplexing (OFDM) (16 point Fast Fourier Transforms (FFT), Inverse Fast Fourier Transform (IFFT) and Cyclic Prefix) and QDDFS. QDDFS generates the sine and cosine values in digital domain and it is optimized in terms of the device utilization with efficient performance and the functionality of rapidly hopping between the different frequencies, faster response time are also achieved. Both in transmitter and receiver, the same QDDFS architecture is used. The Input to the SDR system designed is Text Data which is fed and retrieved in the ASCII Format.

A Compact Design of a Low Frequency Quadrature DDFS with Low Distortion Using Analog Shapers

An analysis and design of a CMOS differential pair and a common source amplifier for shaping a triangular signal into 0-π/4 segments of sine and cosine waveforms are presented. By multiplexing these two shaped outputs, low distortion full sine and cosine signals can be produced at one fourth the frequency of the triangular input. These two circuits can be combined with one DAC and a phase accumulator to form a compact quadrature direct digital frequency synthesizer (Q-DDFS) suitable for generating low distortion sinusoidal signals at low frequency. The shapers are biased by two current generators specially designed to compensate for process parameter variations. MOS dimensional mismatch is also studied. The analog part of the Q-DDFS is synthesized using 0.18-micron n-well CMOS technology. A simulation shows that the circuit consumes 1.3 mW and can generate 19.96 mV 50 kHz sine and cosine signals with spurious free dynamic range (SFDR) of around 50 dBc from a Q-DDFS running at 1.6 MHz.

A direct digital frequency synthesizer based on ROM free algorithm

An ROM free quadrature direct digital frequency synthesizer (DDFS) was proposed in this paper. The proposed DDFS mainly consists of two adders and two multipliers to generate quadrature outputs. The proposed DDFS was implemented in both cell-base library and ALTERA Stratix EP1S40F780C5 FPGA board for verification. The spurious-free dynamic range (SFDR) measured from FPGA board is about 84 dBc on average. The TSMC 0.18 μ m technology is adopted in the cell-based library implementation. The simulated power efficiency is 0.041 mW/MHz averaged for 0.18 μ m technology. The gate count is about 5384 calculated using the design compiler. The maximum clock frequency can reach to 225 MHz.

Quadrature direct digital frequency synthesizers using interpolation-based angle rotation

This paper describes a quadrature direct digital frequency synthesizer (QDDFS) architecture based on a new phase-to-sine conversion technique. The proposed technique uses polynomial interpolation and rotational transformation in a fine/coarse approach, achieving high-resolution output with a wide spurious-free dynamic range (SFDR). The QDDFS with this technique requires small-sized lookup tables and a simple computational engine. The fine/coarse decomposition significantly reduces the size of required lookup tables, and the polynomial interpolation enables accurate approximation of cosine and sine values. Two prototype QDDFS ICs were fabricated in 0.35-/spl mu/m CMOS. The final prototype IC produces 16-b cosine and sine outputs with a spectral purity greater than 100-dB. It has a frequency tuning resolution of 0.03-Hz at a 150-MHz sampling rate and consumes 350-mW with a 3.0-V power supply.

A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values as in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a quadrature DDFS has been implemented using 0.5-/spl mu/m CMOS process and occupies an active area of 1.4 mm/sup 2/. It consumes 8 mW at 100 MHz and operates from a single 2.7-V supply. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.

A frequency-agile single-chip QAM modulator with beamforming diversity

Architecture and circuit design techniques for VLSI implementation of a single-chip quadrature amplitude modulation (QAM) modulator with frequency agility and antenna beamforming characteristics are presented. In order to achieve reliable wireless communication modem function, the single chip all-digital QAM modulator implements various features, including high data rates with bandwidth efficiency, flexibility, meeting a wide variety of user throughput requirements with variable and width and data rates in a multi-user system, and robustness, incorporating diversity and redundancy techniques to guarantee robust communication for various operating environments. The modulator components consist of several digital processing building blocks, including various finite-impulse-response (FIR) filters, an innovative variable interpolation filter, a four-channel frequency translator with quadrature mixer for antenna beamforming diversity, a quadrature direct digital frequency synthesizer (QDDFS), a numerically controlled oscillator (NCO), a QAM formatter, a pseudorandom noise (PN) generator, an x/sinx filter, and a microcontroller interface. An optimized architecture and chip implementation for the variable modulator is derived and evaluated which will support symbol rates from 6 kBaud to 8.75 MBaud continuously and digitally flexible IF frequencies up to 70 MHz with four-channel antenna beamforming function.

Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter

A design technique that uses nonlinear digital-to-analog converter (DAC) for implementing low-power direct digital frequency synthesizer (DDFS) is proposed. The nonlinear DAC is used in place of the ROM look up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. Since the proposed design technique for DDFS does not require a ROM, significant saving in power dissipation results. The design procedure for implementing the nonlinear DAC is presented. To demonstrate the proposed technique, two quadrature DDFSs, one using nonlinear resistor string DACs and the other using nonlinear current-mode DACs, were implemented. For a 3.3-V supply, the resulting power dissipation for both DDFSs are 4 and 92 mW at a clock rate of 25 MHz and 230 MHz, respectively. For both DDFSs, the spurious free dynamic ranges are over 55 dB for low synthesized frequencies.

An 800-MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 μm CMOS

An 800 MHz quadrature direct digital frequency synthesizer (QDDFS4) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc, The frequency resolution is 0.188 Hz with a corresponding switching speed of 5 ns and a tuning latency of 47 clock cycles. The chip is also capable of frequency and phase modulation. ECL-compatible output drivers are provided to facilitate I/O compatibility with other high speed devices. A high gain amplifier at the clock input enables the QDDFS4 chip to be clocked with ac-coupled RF signal sources with peak-to-peak voltage swings as small as 0.5 V. The 0.8 /spl mu/m triple level metal N well CMOS chip has a complexity of 94000 transistors with a core area of 5.9/spl times/6.7 mm/sup 2/. Power dissipation is 3 W at 800 MHz and 5 V.