Quadrature Bandpass Research Articles

Multiband Quadrature Bandpass Sampling

Global navigation systems (GNSS) receivers are designed to be highly accurate. Next generation receivers may also need to provide high flexibility to exploit the probabilities of new specifications and algorithms. Quadrature bandpass sampling (QBPS) RF front-ends offer a possible architecture to meet this requirement. For QBPS, delay offset errors between analog-to-digital converters will introduce phase distortions. Quantification of the effects of these distortions on signal reconstruction was performed and characterized using image rejection ratio (IRR). This article investigates the best delay offset when using QBPS in multiband systems. It first analyzes the combined effect of delay offset error and in-band frequency offset for a single frequency component, then a combined IRR is defined for multiband receivers. Also, a delay offset setting scheme is proposed to maximize the combined IRR. The results show that, for a specific GNSS all-system receiver, the optimal delay offset is 158.7ps in noise-free conditions. Further, the optimal delay offset can be shifted in the presence of sampling jitter.

A 1-MHz-Bandwidth Gm-C-Based Quadrature Bandpass Sigma-Delta Modulator Achieving −153.7-dBFS/Hz NSD With Background Calibration

This paper presents a fifth-order continuous-time Gm-C-based quadrature bandpass sigma-delta ( $\Delta \Sigma$ ) modulator for Internet-of-Things applications. In the presented $\Delta \Sigma $ modulator, a reconfigurable full-scale input amplitude assists the $\Delta \Sigma $ modulator, achieving a wide dynamic range (DR) and a low-noise floor. A following system-level supply voltage and temperature background tracking technique stabilizes the frequency response of the Gm-C-based quadrature bandpass $\Delta \Sigma $ modulator. Furthermore, the 1.5-bit feedback current DAC employs a PN-based semi-self-swapping logic to relax the matching requirement. The prototype $\Delta \Sigma $ modulator was fabricated in a 180-nm CMOS process with an active area of 0.28 mm2. The $\Delta \Sigma $ modulator achieves a total DR of 93.7 dB with the reconfigurable full-scale input amplitude, resulting in a noise spectral density of −153.7 dBFS/Hz with a bandwidth of 1 MHz. The presented $\Delta \Sigma $ modulator consumes 2.0 mW with a power supply of 1.8 V and a sampling frequency of 32 MHz.

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver * * Project supported by the National Natural Science Foundation of China (Nos. 61471245, U1201256), the Guangdong Province Foundation (No. 2014B090901031), and the Shenzhen Foundation (Nos. JCYJ20160308095019383, JSGG20150529160945187).

This paper presents the design and implementation of quadrature bandpass sigma-delta modulator. A pole movement method for transforming real sigma-delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma-delta modulator. The proposed modulator uses sampling capacitor sharing switched capacitor integrator, and achieves a very small feedback coefficient by a series capacitor network, and those two techniques can dramatically reduce capacitor area. Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation. This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and -1 MHz IF with 48 MHz clock. The chip is fabricated with SMIC 0.18 μm CMOS technology, it achieves a total power current of 2.1 mA, and the chip area is 0.48 mm2.

Development of a Low-Complexity, Cost-Effective Digital Beamformer Architecture for High-Frequency Ultrasound Imaging

This paper presents a low-complexity, cost-effective digital beamformer architecture for a high-frequency ultrasound imaging system. The proposed beamformer uses a lookup table and linear interpolation methods for computing the dynamic receive focusing delays and a postfiltering technique to minimize hardware complexity. In the postfiltering technique, channel radio-frequency data having the same fractional delay (i.e., 16f0 resolution) are aggregated prior to interpolation. Thus, only four polyphase structure filters are required in the developed beamformer. In addition, a quadrature bandpass filter that generates an analytic signal is utilized as an interpolation filter; this allows decimation during beam formation and a reduction in computational complexity. The proposed method was evaluated through a 20- [Formula: see text] wire phantom experiment, and the -6-dB lateral and axial resolutions obtained therein were measured and compared with those obtained using a conventional method. The same lateral (165 [Formula: see text]) and axial (80 [Formula: see text]) resolutions at a depth of 5.6 mm were obtained using both the methods, and the proposed method could reduce the beamforming points (i.e., computational complexity) by a factor of the decimation factor (≥4). Images from an excised bovine eye were captured; they showed that the proposed beamformer identified fine anatomical structures such as cornea or iris without compromising the spatial resolution and reduced the computational complexity.

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time $\Sigma \Delta $ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

A fourth-order quadrature bandpass continuous-time sigma–delta modulator for a dual-channel global navigation satellite system (GNSS) receiver is presented. With a bandwidth (BW) of 33 MHz, the modulator is able to digitalize the downconverted GNSS signals in two adjacent signal bands simultaneously, realizing dual-channel GNSS reception with one receiver channel instead of two independent receiver channels. To maintain the loop-stability of the high-order architecture, any extra loop phase shifting should be minimized. In the system architecture, a feedback and feedforward hybrid architecture is used to implement the fourth-order loop-filter, and a return-to-zero (RZ) feedback after the discrete-time differential operation is introduced into the input of the final integrator to realize the excess loop delay compensation, saving a spare summing amplifier. In the circuit implementation, power-efficient amplifiers with high-frequency active feedforward and antipole-splitting techniques are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-b quantizers. These power saving techniques help achieve superior figure of merit for the presented modulator. With a sampling rate of 460 MHz, current-steering digital–analog converters are chosen to guarantee high conversion speed. Implemented in only 180-nm CMOS, the modulator achieves 62.1-dB peak signal to noise and distortion ratio, 64-dB dynamic range, and 59.3-dB image rejection ratio, with a BW of 33 MHz, and consumes 54.4 mW from a 1.8 V power supply.

Study of quadrature FIR filters for extraction of low-frequency instantaneous information in biophysical signals

Quadrature bandpass filters take a real-valued signal and output an analytic signal from which the instantaneous amplitude and phase can be computed. For this reason, they represent a useful tool to extract time-varying, narrow-band information from electrophysiological signals such as electroencephalogram (EEG) or electrocardiogram. One of the defining characteristics of quadrature filters is its null response to negative frequencies. However, when the frequency band of interest is close to 0 Hz, a careless filter design could let through negative frequencies, producing distortions in the amplitude and phase of the output. In this work, three types of quadrature filters (Ideal, Gabor and Sinusoidal) have been evaluated using both artificial and real EEG signals. For the artificial signals, the performance of each filter was measured in terms of the distortion in amplitude and phase, and sensitivity to noise and bandwidth selection. For the real EEG signals, a qualitative evaluation of the dynamics of the synchronization between two EEG channels was performed. The results suggest that, while all filters under study behave similarly under noise, they differ in terms of their sensitivity to bandwidth choice. In this study, the Sinusoidal filter showed clear advantages for the estimation of low-frequency EEG synchronization.

QBPS in RF front‐ends

Quadrature bandpass sampling (QBPS) offers a reduced complexity alternative to sampled quadrature (Q) downconversion. However, if the in-phase and quadrature sequences produced are reconstructed at the baseband in the same manner, distortion will result. The effects of this distortion are examined with a view to establish the best way to process the QBPS sequences.

A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> ADC With AntiPole-Splitting Opamp and Digital <inline-formula> <tex-math notation="LaTeX">$I$ </tex-math></inline-formula>/<inline-formula> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> Calibration

A dual-mode second-order reconfigurable quadrature bandpass continuous-time delta–sigma modulator is presented for a low-IF global navigation satellite system receiver to simplify the entire architecture. The proposed modulator is capable of supporting both narrowband of 5-MHz bandwidth (BW) and wideband of 20-MHz BW. An amplifier topology with active feed-forward and antipole-splitting compensation schemes is proposed. The flexible amplifiers in active- RC integrators and preamplifiers in comparators are implemented with power scaling technique to effectively adjust the power consumption for both BWs. A 1-bit digitally switched current digital-to-analog converter structure with gate-leakage compensation and low-latency dynamic element matching is proposed to cover large current variations and mitigate the gate-leakage issue. Digital $I$ / $Q$ self-calibration algorithm is realized to improve the image-rejection ratio (IRR). Implemented in 65-nm CMOS, the $\Delta \Sigma $ modulator achieves 67.8-/61.4-dB dynamic range, 65.9-/53.7-dB signal-to-noise-plus-distortion ratio, and >60-dB IRR after calibration across 5-/20-MHz BW with center frequencies of 4/12 MHz, respectively. Powered by a 1.2 V supply, the modulator only consumes 4.2/8.1 mW, resulting in measured figure-of-merits of 0.26/0.51 pJ/conversion step.

Interference rejection in quadrature band-pass $$\varSigma \varDelta $$ Σ Δ modulators

Interference is a major concern in surface acoustic wave-less receiver architectures. This paper presents an architectural solution to design a quadrature band-pass $$\varSigma \varDelta $$ΣΔ modulator in presence of interference signals. These interferences are rejected by using the built-in signal transfer function (STF) filtering action inside the quadrature modulator. The implementation of the STF filtering is achieved by means of feed-forward paths and does not require any additional active blocks. Simulations at the behavioral level on different design examples verify the architecture implementation and the effectiveness of the approach.

A High Image-Rejection SC Quadrature Bandpass DSM for Low-IF Receivers

The quadrature bandpass Delta-Sigma modulator (QBDSM) is widely used in low-IF wireless receivers. In general, every coefficient in a QBDSM is complex. For a complex coefficient realized by real circuit blocks, there are always two circuit paths (I and Q) for both its real and imaginary parts (if non-zero). Mismatches between the two circuit paths of any complex coefficient in the QBDSM can lead to the following problems: 1) interference at the image frequency to fold into the signal band; 2) the unshaped quantization noise at the image frequency to leak into the signal band; and even 3) the mirrored image of the desired signal around its center frequency (self-image) to appear in some implementations. This paper analyzes the I/Q mismatch effects in a switched-capacitor QBDSM and proposes chopper and circuit multiplexing techniques to mitigate these problems. A prototype QBDSM was fabricated in a 0.18 μm CMOS, with a measured image rejection ratio no less than 73 dB, a self-image rejection ratio of 72 dB, and no observable image quantization noise.

12-channel receive array with a volume transmit coil for hand/wrist imaging at 7 T

To develop a coil configuration for high-resolution imaging of different regions of the hand and wrist at 7 T. A quadrature bandpass birdcage and a 12-channel high density receive array were developed for imaging metacarpus and wrist. Workbench and magnetic resonance imaging (MRI) measurements were done to characterize the coil and obtain in vivo images. Electromagnetic simulations were performed to assess the uniformity of transmit profile and calculate the specific absorption rate (SAR). The results obtained show that the constructed transmit coil can be used in combination with receive arrays, without the need to retune the same. The developed wrist array was used to produce images of ultrahigh resolution (0.19 × 0.19 × 0.5 mm(3) ), revealing fine anatomical details. Simulations show that a near-uniform transmit profile is possible throughout the hand. No inhomogeneities were observed in the transmit profile, unlike a human head or abdomen at 7 T, due to the small volume of the hand and its low conductive regions. While transceive arrays are usually preferred at 7 T due to issues related to decrease in wavelength, it is shown in this study that with regard to hand-imaging optimized high-density receive arrays are a good solution to obtain images of extremely fine resolution of different regions.

A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver

A second-order multi-bit quadrature bandpass continuous-time delta-sigma modulator (QBP-CTDSM) employing a power-scaling technique (PST) and a quadrature mismatch scrambler (QMS) for a tri-mode GSM-EDGE/UMTS/DVB-T low-IF receiver is reported in this paper. This modulator employs operational amplifiers with PST to optimize power consumption among the tri-mode operation. In addition, the modulator incorporates the proposed QMS to mitigate the mismatch between the I/Q multi-bit DACs. Fabricated in a 0.18-μm CMOS process, the proposed QBP-CTDSM achieves 81/61.2/60.9 dB SNDR across 270- kHz/5-MHz/8-MHz bandwidth. The bandpass center frequency is programmable from 500 kHz to 12 MHz. Measured from a 1.8-V supply voltage, the modulator power consumptions are 4.9/8.9/12.1 mW for the GSM-EDGE/UMTS/DVB-T modes, respectively, which result in FOMs of 0.99/0.95/0.84 pJ/conversion. The measurement results also show that the QBP-CTDSM achieves image rejection ratios better than 55 dB for all modes.

Tunable Mismatch Shaping for Quadrature Bandpass Delta-Sigma Data Converters

Quadrature bandpass delta-sigma data converters are widely used in low-IF receiver applications where high linearity is required over a narrow bandwidth. A quadrature delta-sigma modulator with multibit quantization requires a digital-to-analog converter (DAC) for each of the in-phase (I) and quadrature (Q) paths. Device mismatch errors in the DAC can seriously degrade overall converter performance by adding I/Q path-mismatch and distortion. Mismatch noise shaping is an established technique for overcoming these limitations in a complex DAC, but usually anchors the signal band to a fixed frequency location. In order to apply mismatch shaping to applications that require tunable signal band locations, this paper presents a technique that allows the center frequency of the mismatch noise shaping transfer function through the complex DAC to be adjustable over the entire Nyquist range.

A one-path subsampling quadrature receiver based on a ΣΔ modulator with distributed resonators

This article presents experimental results of a quadrature bandpass sigma---delta (ΣΔ) modulator based on distributed resonators. The modulator employs transmission lines and transconductors as main components and does not require switches in the loop filter as in the case of switched-capacitor (discrete-time) filters. In addition, the proposed complex modulator does not require a quadrature mixer in the receiver. As main feature, the modulator architecture introduces an innovative way to produce the I and Q outputs that is immune to path mismatch due to the sharing of all the analog circuitry for both paths. The one-bit second-order modulator ADC is able to convert IF signals at fs/2 and 3fs/2 (fs = 50 MHz), achieving an ENOB = 10 bits within a 1 MHz signal bandwidth. Therefore the modulator may be feasible for the typical IF frequencies used in cellular base stations. Furthermore, it provides an image rejection grater than 70 dB. The 0.35 μm BiCMOS chip consumes 28 mW at 3.3 V supply voltage.

Quadrature Bandpass Sampling Rules for Single- and Multiband Communications and Satellite Navigation Receivers

In this paper, we examine how existing rules for bandpass sampling rates can be applied to quadrature bandpass sampling. We find that there are significantly more allowable sampling rates and that the minimum rate can be reduced.

A Current Reuse Quadrature GPS Receiver in 0.13 $\mu$m CMOS

A fully-integrated quadrature low-IF L1-band GPS receiver consumes only 6.4 mW in 0.13 μm CMOS. The RF front-end features a gate-modulated quadrature VCO for low phase noise and accurate quadrature phase signal generation. It merges the LNA, quadrature mixer, and quadrature VCO in a single current-reuse stacked topology that provides a conversion gain 42.5 dB with a power consumption of 1 mW. A continuous-time (CT) quadrature bandpass sigma-delta analog-to-digital converter (ADC) provides inherent anti-alias filtering, which simplifies the overall system. The second-order CT ΣΔ ADC achieves 65 dB dynamic range and dissipates only 4.2 mW using resistor DAC feedback. The receiver exhibits an NF of 6.5 dB and an IIP3 of - 30 dBm; the PLL phase noise is -110 dBc/Hz @ 1 MHz frequency offset with quadrature error less than 1°.

Correction to “A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 $\mu$m CMOS” [Mar 09 891-900

In the above titled paper (ibid., vol. 44, no. 3, pp. 891-900, Mar 09), an error was made in Fig. 15. The corrected figure is presented here.

A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 $\mu$m CMOS

Quadrature bandpass SigmaDelta modulators based on polyphase filters are suited for analog-to-digital conversion in GSM/EDGE low-IF receivers. This paper presents a continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulator with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology - which is a desirable solution for implementation in low power applications. A new compensation scheme for the polyphase filter is proposed. The summation of feedforward signals is implemented by weighted capacitors, without the necessity of any additional active components. The effectiveness of the proposed architecture is proved on a test chip which was designed in a standard 0.25 mum CMOS technology. The designed SigmaDelta modulator has a power consumption of 2.7 mW at 1.8 V supply voltage, a dynamic range of 90.3 dB and a peak SNDR of 86.8 dB. The chip area is 0.5 times 1.4 mm2 including pads.

A Polyphase Filter Design for Continuous-Time Quadrature Bandpass Sigma–Delta Modulators

This paper presents a strategy for successful polyphase-filter design for continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulators. Based on a low-pass filter with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology - which is suited for implementation in low-power applications - analytical equations are derived. A new compensation scheme is proposed and implemented by cross-coupling additional resistors, without the necessity of extra-active components. Translation to intermediate frequency in second- and fourth-order polyphase filters with the proposed compensation scheme are compared to analytical considerations and simulation. Nonlinearities introduced by mismatch of feedforward coefficients and finite gain-bandwidth of amplifiers are considered.

Mismatch Insensitive Double-Sampling Quadrature Bandpass $\Sigma\Delta$ Modulation

In a double-sampling quadrature bandpass sigma-delta modulator, path mismatch between the double-sampling branches and between the I/Q paths occurs. In this paper, an analytical study is presented which shows that this causes quantization noise and input signals to fold from the image band into the signal band and that this also results in a self-image component. To reduce the folding from the image band, a novel resonator is presented. This resonator has a bilinear input circuit so that noise and signals exhibits first-order shaping before folding in the band of interest. Next, three different modulator architectures based on the novel resonator are introduced. Finally, the remaining problem of self-image is tackled with a simple, yet efficient offline calibration strategy. Various design examples are shown and simulated to illustrate and prove the effectiveness of the proposed architectures and methods.