Quad Full HD Research Articles

An Approximate HEVC Intra Angular Prediction Hardware

In this paper, an approximate High Efficiency Video Coding (HEVC) intra angular prediction technique is proposed for reducing area of HEVC intra prediction hardware. The proposed approximation technique uses closer neighboring pixels instead of distant neighboring pixels in intra angular prediction equations. It causes 0.0569% bit rate increase and 0.0028 dB PSNR loss on average. In this paper, an approximate HEVC intra angular prediction hardware implementing the proposed approximation technique is also proposed. FPGA and ASIC implementations of the proposed approximate hardware can process 24 and 40 quad full HD (3840 × 2160) video frames per second, respectively. The proposed approximate HEVC intra angular prediction hardware is the smallest and the second fastest HEVC intra prediction hardware in the literature. It is ten times smaller and 20% slower than the fastest HEVC intra prediction hardware in the literature.

Approximate HEVC Fractional Interpolation Filters and Their Hardware Implementations

High efficiency video coding (HEVC) fractional interpolation algorithm has very high computational complexity. In this paper, two approximate HEVC fractional interpolation filters are proposed. They significantly reduce computational complexity of HEVC fractional interpolation with a negligible PSNR loss and bit rate increase. In addition, two approximate HEVC fractional interpolation hardware are proposed. They, in the worst case, can process 45 quad full HD ( ${3840\times 2160}$ ) fps. They consume up to 67.1% less energy than original HEVC fractional interpolation hardware. Therefore, they can be used in consumer electronics products that require a low energy HEVC encoder.

Quad Full-HD Transform Engine for Dual-Standard Low-Power Video Coding

Transform engine is a critical part of the video codec, and increased coding efficiency often comes at the cost of increased complexity in the transform module. In this work, we propose a shared transform engine for H.264/AVC and VC-1 video coding standards, using the structural similarity and symmetry of the transforms. An approach to eliminate an explicit transpose memory in 2-D transforms is proposed. Data dependency is exploited to reduce power consumption. Ten different versions of the transform engine, such as with and without hardware sharing and with and without transpose memory, are implemented in the design. The design is fabricated using commercial 45-nm CMOS technology, and all implemented versions are verified. The shared transform engine without transpose memory supports Quad Full-HD (3840 × 2160) video encoding at 30 fps, while operating at 0.52 V, with a measured power of 214 μ W. This highly scalable design is able to support 1080 p at 30 fps, while operating down to 0.41 V, with measured power of 79 μW and 720 p at 30 fps, while operating down to 0.35 V, with measured power of 43 μW. Hardware sharing saves 30% area compared with individual H.264 and VC-1 implementations combined. Eliminating an explicit transpose memory using a 2-D (8 × 8) output buffer reduces area by 23% and power by 26%. Ideas proposed here can potentially be extended to future video coding standards such as HEVC.

A Highly Parallel and Scalable CABAC Decoder for Next Generation Video Coding

Future video decoders will need to support high resolutions such as Quad Full HD (QFHD, 4096 × 2160) and fast frame rates (e.g., 120 fps). Many of these decoders will also reside in portable devices. Parallel processing can be used to increase the throughput for higher performance (i.e., processing speed), which can be traded-off for lower power with voltage scaling. The next generation standard called High Efficiency Video Coding (HEVC), which is being developed as a successor to H.264/AVC, not only seeks to improve the coding efficiency but also to account for implementation complexity and leverage parallelism to meet future power and performance demands. This paper presents a silicon prototype for a pre-standard algorithm developed for HEVC (“H.265”) called Massively Parallel CABAC (MP-CABAC) that addresses a key video decoder bottleneck. A scalable test chip is implemented in 65-nm and achieves a throughput of 24.11 bins/cycle, which enables it to decode the max H.264/AVC bit-rate (300 Mb/s) with only a 18 MHz clock at 0.7 V, while consuming 12.3 pJ/bin. At 1.0 V, it decodes a peak of 3026 Mbins/s for a bit-rate of 2.3 Gb/s, enough for QFHD at 186 fps. Both architecture and joint algorithm-architecture optimizations used to reduce critical path delay, area cost and memory size are discussed.