Quad Flat No-lead Research Articles

Analytical thermal resistance network model for calculating each mean die temperature of the multi-chips module combined with quad flat no-leads packaging

With the rapid advancement of next-generation communication technology, traditional Quad Flat No-leads (QFN) packaging is facing challenges to meet functional requirements. Due to its high integration and excellent thermal performance, the Multi-chips Module combined with Quad Flat No-leads (MCM-QFN) packaging is gaining popularity. However, the structural complexity of MCM-QFN packaging and the thermal coupling effect between multiple dies make it challenging to analyze the steady-state thermal distribution of MCM-QFN packaging, which is necessary for assessing the reliability and optimizing the layout design of the multi-chips module. By analyzing the heat dissipation path from each die to the ambient, this paper proposes an analytical thermal resistance network model for calculating each mean die temperature of MCM-QFN packaging. The thermal coupling effect among the multi-chips, the thermal spreading resistance between critical layers, and the boundary conditions and cooling conditions are all considered. All thermal resistances in the model are expressed analytically, and the mean temperature of each chip can be calculated within 0.1 s using MATLAB programming. To validate the accuracy of the proposed model, finite element method (FEM) simulations are conducted to provide a reference for the mean temperature of each chip under four sets of thermal conditions. The data comparison demonstrates that the analytical model is fast and accurate in calculating each mean die temperature of MCM-QFN packaging, with a maximum error of 3.72%, and the calculation speed increased by about 600× compared to that of FEM simulation. Furthermore, the analytical model is able to offer a direction for optimizing the layout design and material selection of MCM-QFN packaging.

Metal Additive Microfabrication of System-in-Package with Embedded Microfluidic Thermal Management for Heterogeneous Integration with Semiconductor Dies

The scaling of components on a single semiconductor chip has enabled the doubling of performance every 2 years as per Moore’s law, and has been possible due to the miniaturization of individual components. A significant decrease in transistor gate length and increase in component density has also introduced an increase in power density. Hence, there is a dire need for embedded thermal management of these systems-on-chips (SoCs) to remove waste heat. In this work, the metal additive microfabrication of a system-in-package (SiP) package with multiple pads for quad flat no-lead (QFN) packaging and a microfluidic channel and pin fin heat sinks for thermal management are presented. This work introduces heterogeneous integration (integration of separately manufactured components into a SiP for improved functionality) of SiPs fabricated using additive microfabrication to clean-room-fabricated integrated circuits (ICs) for improved functionality in terms of the thermal management of high-power density SoCs. The packages have been fabricated via a metal additive manufacturing technique, direct metal laser sintering (DMLS), using 316L stainless steel as the precursor powder. The work also opens doors to the fabrication and integration of metal microsystems using DMLS to complement semiconductor manufacturing and packaging processes. The use of air or water as the coolant for the packaging devices decreased the thermal resistance from 5.25°C/W for the conventional packages to 2.02°C/W for a flow rate of 84 mL/min when subjected to a constant heat flux. The average surface temperature also decreased from 45.61°C to 29.23°C for the same parameter. This article details the material characteristics and thermal performance of the metal additively microfabricated SiPs.

QUAD FLAT NO-LEAD PACKAGE WITH DIFFERENT THERMAL PROFILES AND SOLDER PAD FINISHING FOR VOID MINIMIZATION

Voiding in solder joints is a common problem that occur in electronic packaging, specifically for bottom terminated component (BTC). Quad Flat No-Lead (QFN) is a good example of BTC component that susceptible to void. Thus, QFN component thermal pads were used as the test vehicle in this voiding assessment. The objectives of this study are to analyze the influence of the variables from every parameter evaluated in the experiment on voiding area in QFN thermal pad solder joint and obtain the best combination of variables that can minimize the total void area percentage inside QFN thermal pad solder joint down to below 5%. In this study, several variables and their impacts on voiding based on the literature review were studied. No clean lead-free solder paste of SAC305 composition was employed in this experiment. Various stencil patterns were tested, including Window-Pane, Round, and Triangle/Polygon. The influence of pad surface finishing of the test board on the voiding reduction was analyzed in this study. The effects of convection reflow of various profiles and atmospheres were also considered. All the variables were setup for the experiment execution which begins by solder paste printing, solder paste inspection, component pick & place, convection reflow soldering, Xray inspection, void data extraction & analysis, and finally void results compilation. The results shown that reflow profile Ramp-To-Spike (RTS) Long Reflow Time High Peak Temperature gave lesser void area % than Ramp-Soak-Spike (RSS) Long Soak and RTS Normal profiles.

Design, fabrication, characterization and reliability study of CMOS-MEMS Lorentz-force magnetometers

This article presents several design techniques to fabricate micro-electro-mechanical systems (MEMS) using standard complementary metal-oxide semiconductor (CMOS) processes. They were applied to fabricate high yield CMOS-MEMS shielded Lorentz-force magnetometers (LFM). The multilayered metals and oxides of the back-end-of-line (BEOL), normally used for electronic routing, comprise the structural part of the MEMS. The most important fabrication challenges, modeling approaches and design solutions are discussed. Equations that predict the Q factor, sensitivity, Brownian noise and resonant frequency as a function of temperature, gas pressure and design parameters are presented and validated in characterization tests. A number of the fabricated magnetometers were packaged into Quad Flat No-leads (QFN) packages. We show this process can achieve yields above 95 % when the proper design techniques are adopted. Despite CMOS not being a process for MEMS manufacturing, estimated performance (sensitivity and noise level) is similar or superior to current commercial magnetometers and others built with MEMS processes. Additionally, typical offsets present in Lorentz-force magnetometers were prevented with a shielding electrode, whose efficiency is quantified. Finally, several reliability test results are presented, which demonstrate the robustness against high temperatures, magnetic fields and acceleration shocks.

Wettable flank routable thin MicroLeadFrame for automotive applications

Driven by the higher power density and harsh environments in automotive, leadframe package has been varied to meet the higher requirement of reliability and integration. Quad Flat No-Lead (QFN) packages is known to provide the small form factor, and adequate for the high power package system. However, due to its wet pad characteristics, the solder volume is thin without fillet endangering the structural reliability. Therefore, it is very important to ensure structural integrity by constructing sound solder fillet, and it is mandatory for industry to inspect visually the soldering state after the bonding process. Wettable flank QFN is designed for this particular purpose. In this study, the routable thin MicroLeadFrame®, an wettable flank technology which allows easy process by employing chemical etching yet enables the side solder visible inspection for fine lead pitch, is introduced and explored. Process to achieve the wettable flank structure was developed, and the reliability was studied through Automotive Electronics Council (AEC) reliability test under package level and board level. Also, mechanical shear test and simulation was carries out to verify the wettable flank structure feasibility to the automotive electronics packaging by demonstrating excellent reliability performances.

Application of deuterium oxide (D2O) isotope tracing technique for encapsulated QFN failure analysis

Polymer encapsulated components are universally used in consumable applications. However, polymer encapsulants for packages commonly are non-hermetic. The polymer encapsulants can absorb moisture from atmosphere which will post a risk to the package reliability. In this study, a type of polymer encapsulated Quad Flat No-Lead (QFN) package encountered electricity leakage after Highly Accelerated Stress Tests (HAST) 96 h. Although it is suspected that penetration of moisture into the encapsulated package caused electrical leakage failure, there is no direct evidence to prove this assumption. Traditional X-ray and Scanning Acoustic Microscopy (C-SAM) techniques cannot detect any defect of the package due to their detection limit.To solve above issues, this study employed a new deuterium oxide (D2O) isotope tracing method. The encapsulated package underwent highly Accelerated Stress Tests (HAST) with D2O, and D signal of the sample was analysed by Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS). The results showed that D localized at the failure area where leakage occurred. It is direct evidence to show it is a moisture-induced leakage.

Understanding the Cause and Effect of Bent Side Rail in Molding Process

During processing of Quad Flat No-lead (QFN) on the production line, it has been observed that strips were found with bent rails after the molding process. Mold is a process in the semiconductor industry where package encapsulation happens by filling the cavities with molding compound, depending on the required package thickness. Succeeding processes of post-mold cure, strip etching, and laser marking were not affected by the encountered bent rails at mold but singulation process feedback that the affected strips prompted jig alignment errors which prevents the strip to be successfully auto processed at jig saw singulation. The problem on hand have encouraged the authors to understand the cause of bent rails thru process mapping and validation of its effect on the downstream processes.

Antenna-in-Package (AiP) Using Through-Polymer Vias (TPVs) for a 122-GHz Radar Chip

High-performance IC-to-antenna interconnection is one of the key enablers for the mass production of high-end millimeter wave (mmW) radar systems above 100 GHz. In this work, a radar system with an on-package antenna array working at 122 GHz is presented. The antenna is placed on top of the molded package and the antenna-to-chip interconnection is realized by through-polymer via (TPV) technology. The detailed fabrication process of the radar antenna-in-package (AiP) with TPV is discussed. The results from the functional tests of the radar AiP are presented and benchmarked to a commercial quad-flat no-leads (QFN) package with an open antenna cavity. The detection margin between the echo signal and the constant false alarm rate (CFAR) threshold is approximately 10 dB higher for the TPV radar AiP compared with the benchmarked commercial QFN package.

The Effect of Acrylic Conformal Coating in the Reliability of Solder Joints

During the product life, electronic components are subjected to environmental conditions, such as humidity or temperature fluctuations. Solder joints, which allow the electrical and mechanical connection, are one of the most critical spots to have failures due to environmental conditions. Conformal coating, a thin layer that encapsulates all components and consequently solder joints, is one of the techniques that allows the protection of the component against these detrimental effects. Nevertheless, the application of conformal coating has not been recommended in some components, namely in ball grid arrays (BGAs) and quad-flat-no-leads (QFN), since it can compromise the reliability of their solder joints when exposed to temperature fluctuations. Herein, by using an accelerative test, the reliability of BGA- and QFN-coated solder joints with an acrylic conformal coating was studied. A thermal cycle test of temperature ranging from −40 °C to +125 °C comprising 837 cycles demonstrated no failures (confidence level of 0.99; <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R = 4$ </tex-math></inline-formula> ppm/year; <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta = 3$ </tex-math></inline-formula> ) to occur due to acrylic conformal-coating application. However, the solder joints analysis indicated that conformal coating causes an excess of deformations on solder joints, compromising their reliability. Therefore, this study suggests that this acrylic conformal coating is not suitable for these electronic components.

Smarter Temperature Setup for Reflow Oven to Minimize Temperature Variation Among Components

The thermomechanical reliability of surface mount components (SMCs) is closely related to the reflow soldering process. With the rise of board complexity, an optimal reflow profile must consider the mix of large and small components, the density of the components on the board, and the board dimensions. It has been a significant challenge to achieve uniform temperature on SMCs with different sizes and different thermal masses, such as capacitors, transistors, quad-flat no-leads (QFN), and ball grid array (BGA) packages. To reflow large components such as BGA packages, the minimum reflow temperature should be reached, meanwhile, the temperature should not exceed the damaging temperature of the smaller or heat-sensitive components. The recommended reflow profile is defined as a band or process window. To achieve good quality soldering, the temperature applied to the solder under varied sizes of components should be within the recommended band. This article introduces a numerical method based on a compact model to predict the reflow profile for bulky BGA packages. The impinging gas temperature is used as the boundary condition to predict the temperature distribution throughout a board with different sized components. The proper oven temperature setting to achieve the ideal profiles is obtained finally.

Effect of high-frequency PCB laminate on thermal cycling behavior of electronic packaging structures

PurposeAs the solution to improve fatigue life and mechanical reliability of packaging structure, the material selection in PCB stack-up and partitioning design on PCB to eliminate the electromagnetic interference by keeping all circuit functions separate are suggested to be optimized from the mechanical stress point of view.Design/methodology/approachThe present paper investigated the effect of RO4350B and RT5880 printed circuit board (PCB) laminates on fatigue life of the QFN (quad flat no-lead) packaging structure for high-frequency applications. During accelerated thermal cycling between −50 °C and 100 °C, the mismatched coefficients of thermal expansion (CTE) between packaging and PCB materials, initial PCB warping deformation and locally concentrated stress states significantly affected the fatigue life of the packaging structure. The intermetallics layer and mechanical strength of solder joints were examined to ensure the satisfactorily soldering quality prior to the thermal cycling process. The failure mechanism was investigated by the metallographic observations using a scanning electron microscope.FindingsTypical fatigue behavior was revealed by grain coarsening due to cyclic stress, while at critical locations of packaging structures, the crack propagations were confirmed to be accompanied with coarsened grains by dye penetration tests. It is confirmed that the cyclic stress induced fatigue deformation is dominant in the deformation history of both PCB laminates. Due to the greater CTE differences in the RT5880 PCB laminate with those of the packaging materials, the thermally induced strains among different layered materials were more mismatched and led to the initiation and propagation of fatigue cracks in solder joints subjected to more severe stress states.Originality/valueIn addition to the electrical insulation and thermal dissipation, electronic packaging structures play a key role in mechanical connections between IC chips and PCB.

Ka-대역 QFN 패키지의 본딩 와이어 분석 및 설계

In this study, an equivalent model of bonding wire used in the Ka-band quad flat no-lead (QFN) package was proposed. The proposed equivalent model was constructed using resistors and inductors according to the length of the bonding wire and the mutual inductance between the multi-bonding wires. For verification, the S-parameters derived from the equivalent model were compared with the three-dimensional (3D) electromagnetic simulation results. Moreover, a Ka-band QFN package was designed using the proposed equivalent model. The number and length of the bonding wires required to optimize the return loss (S11) and the insertion loss (S21) of the designed Ka-band QFN package were derived and applied. In the fabricated Ka-band QFN package, the S11 and S21 were measured to be −26 dB to −1.8 dB at 29 GHz, respectively, and it was confirmed that the measurement results were similar to the simulation results.

A 24-GHz Fully Integrated CMOS Transceiver for FMCW Radar Applications

A 24-GHz fully integrated frequency-modulated continuous wave (FMCW) direct conversion transceiver, implemented in a 55-nm low-power CMOS technology with a maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm {T}}$ </tex-math></inline-formula> of 190 GHz in typical operating conditions and packaged in a 5-mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 5-mm 32-lead quad-flat no-leads (QFN) package, is presented in this article. The single-chip transceiver uses a single 2.5-V supply while all the core circuits are powered by integrated regulators. The complex low-noise transductor in the receiver uses a quadrature hybrid to generate quadrature signals in the receiving front-end. The analog signal processing circuits including high-pass filters, low-pass filters, and programmable amplifiers are implemented following the receiver front-end circuitry. The FMCW signals are generated by an on-chip 24-GHz fractional-N frequency synthesizer. The synthesizer is completely integrated with the transceiver and provides built-in digital frequency modulation to generate chirping signals for the down-conversion local oscillator (LO) and the transmitted signals. The transmitter is composed of a balanced class-AB power amplifier driven by the FMCW signals from the frequency synthesizer.

A 10-Gb/s Driver/Receiver ASIC and Optical Modules for Particle Physics Experiments

We present the design and test results of a Drivers and Limiting AmplifierS ASIC operating at 10 Gb/s (DLAS10) and three miniature optical transmitter/ receiver/transceiver modules (MTx+, MRx+, and MTRx+) based on DLAS10. DLAS10 can drive two transmitter optical subassemblies (TOSAs) of vertical cavity surface emitting lasers (VCSELs), receive the signals from two receiver optical subassemblies (ROSAs) that have no embedded limiting amplifiers (LAs), or drive a VCSEL TOSA and receive the signal from a ROSA, respectively. Each channel of DLAS10 consists of an input continuous time linear equalizer (CTLE), a four-stage LA, and an output driver. The LA amplifies the signals of variable levels to a saturation amplitude of 800 mV (peak-peak). The output driver drives VCSELs or impedance-controlled traces. DLAS10 is fabricated in a 65-nm CMOS technology. The die is 1 mm ×1 mm. DLAS10 is packaged in a 4 mm ×4 mm 24-pin quad-flat no-leads (QFNs) package. DLAS10 has been tested in MTx+, MRx+, and MTRx+ modules. Both measured optical and electrical eye diagrams pass the 10-Gb/s eye mask test. The input electrical sensitivity is 40 mVp-p, while the input optical sensitivity is -12 dBm. The total jitter of MRx+ is 29 ps (P-P) with a random jitter of 1.6 ps (rms) and a deterministic jitter of 9.9 ps. Each MTx+/MRx+ module consumes 82.6 and 174.4 mW/ch, respectively.

2.6-GHz Integrated LDMOS Doherty Power Amplifier for 5G Basestation Applications

This letter presents a compact output combining network for a packaged integrated asymmetric Doherty power amplifier (DPA) by taking advantage of device drain source capacitance, Cds and package parasitic components. A new method is introduced to/of/for absorbing part of the peaking amplifier's C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> ds</sub> into the impedance transformer, thus extending the C- L- C-based “ C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> ds</sub> -absorption” technique to two-way asymmetric DPAs. Based on the proposed combining network, a two-stage laterally-diffused metal-oxide semiconductor (LDMOS) integrated asymmetric DPA was designed and fabricated at 2.6 GHz. The fabricated RF integrated circuit (RFIC) is mounted in a quad flat no-lead (QFN) package. Under a single-tone continuous-wave (CW) signal at 2.6 GHz, the DPA achieves a peak power of 46 dBm, a linear gain of 31.7 dB, and a 48% power-added efficiency (PAE) at 8-dB output power back-off (OBO). The DPA also demonstrates good linearizability by meeting the 5G spectrum mask and achieving a digital predistortion (DPD) corrected adjacent channel power ratio (ACPR) better than -51.5 dBc for 160-MHz long-term evolution (LTE).

Assembly Wirebond Process Solution for Mitigating Leadframe Bouncing on Multi-Die QFN Device

Modification and improvement of an existing tooling design in semiconductor packaging industry has been a usual practice, to enhance the current setup and to provide a solution to a specific assembly problem. This paper discusses the solution in eliminating the smashed ball defect occurrence observed after wirebond process. Smashed ball is usually encountered if the unit is unstable and creates a bouncing effect during wirebond process. It is therefore important to mitigate this micro-bouncing effect by analyzing the package design and the window clamp and top plate (WCTP). The objective is to increase the stability of the unit during wirebonding, especially for quad-flat no-leads (QFN) package with no tape. To achieve this, the solution is to alter the vacuum hole design of the top plate from single hole per unit to multiple holes of varied sizes per unit. Ultimately, after changing the design of the top plate, the micro-bouncing encountered during wirebond process was significantly reduced. This in turn created a consistent ball formation in all bonded wires. The comparative data presented in this paper confirmed the effectivity of the redesigned WCTP. For future works and studies, the improvement and learnings could be used on devices with comparable configuration.

Glass Die Ink Marking Media Selection for a Robust Glass Attach Process

Glass material used on a semiconductor device for isolating currents are one of the new breakthroughs of the modern world. Challenges are inevitable due to its complex characteristics and unique appearance. The study focuses on the phenomenon of reject glass die unrecognized, picked and bonded by die attach machine on good units of the semiconductor quad-flat no-leads (QFN) device in focus. This QFN device utilizes glass die as interposer on two active dice that separates the dielectric current of each die. During die attach process, machine photo recognition system failed to recognize and detect the glass die reject marking due to its unique transparent design and will be attached on good units. Thus, resulting to gross rejection and low process yield. Practical solutions to prevent the said phenomenon are simulated and determined by performing selection of variables like the contrast of the reject mark related to the product structure and compatibility through statistical analysis. The improvement drives to promote process robustness and scrap reduction that will help the manufacturing to be competitive through innovative resolutions on problems.

Addressing the Broken Wire Issue during the Assembly Manufacturing of QFN Leadframe Device

The integrity of the assembly wirebond process’ 2nd bond poses a big challenge for semiconductor manufacturing of quad-flat no-leads (QFN) devices, particularly on multiple wires on a lead. These devices are vulnerable to induce or obtain broken wire at heel defect. This type of defect is an abnormality in the formation of the stitch, mostly a crack or fracture seen on the facade of the stitch. Normally, it happens when there is too much vibration or transfer of ultrasonic generator (USG) power combined with high bonding force on 2nd bond. In the case of leads with common wires, broken wire at heel could also happen through excessive USG application resulting to transfer of resonance on adjacent wires. This paper presents a better understanding and analysis done to provide an adequate and appropriate solution to broken wire at heel issue.

Epoxy Fillet Height Study of Tapeless QFN Leadframe Package on Different Diebonders

The paper focused on the evaluation of quad-flat no-leads (QFN) device in tapeless leadframe technology on different diebonder platforms to achieve an acceptable fillet height performance. The study was narrowed down into two main machines with the objective of attaining a fillet height of less than 75 % for small die. Eventually, the fillet height requirement was achieved by both diebonder platforms, hence, these machines could be used for future works on devices with similar requirement.

Off-centered Ball Resolution Through Multi-hole Process Plate Implementation at Wirebond Process

With the continuous trend of new technologies in semiconductor manufacturing assembly, challenges and issues are unavoidable. This paper presents the modification and improvement done on the process plate design to eliminate the bouncing effect of the silicon die that leads to off-centered ball (OCB) reject during the formation of wire on a quad flat no-leads (QFN) device. The panel type single-row process plate cannot totally vacuum the warped leadframe and this is resulting to off-centered ball. Through changing the panel type single-row process plate to panel type multi-hole process will have a strong vacuum sucked underneath the leadframe and eliminates the occurrence of off-centered ball. Future works could use the improved process plate design for devices of similar configuration.