QR Decomposition Architecture Research Articles

FPGA Implementation of Sparsity Independent Regularized Pursuit for Fast CS Reconstruction

Sparse recovery algorithms are integral to compressed sensing (CS) as they facilitate the reconstruction of higher dimensional signals from sub-Nyquist measurements. Although Orthogonal Matching Pursuit (OMP) has been ubiquitously adopted in hardware implementations to curb the computational complexity of CS recovery, increasing sparsity levels incur higher reconstruction costs. Sparsity independent regularized pursuit (SIRP) is a recent algorithm that employs parallel index selection and regularization to curtail the number of iterations required to reconstruct the signal and thereby enhance the reconstruction speed. This paper proposes a novel reformulation of the SIRP algorithm from the hardware perspective, incorporating a cheaper regularization strategy and a modified Gram-Schmidt (MGS) based incremental QR decomposition (QRD) approach. The proposed design incorporates an iterative QRD architecture with feedback circuitry to exploit the parallelism of the triangularization step in MGS. Additionally, a fast inverse square block circumvents the need for parallel divider blocks giving considerable hardware and latency savings. The design reuses the iterative QRD block to implement the interdependent computations of the algorithm by sophisticated scheduling techniques. The proposed implementation on a Xilinx Virtex Ultrascale FPGA can recover 1024-dimensional signals from 25% measurements within <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$77~\mu \text{s}$ </tex-math></inline-formula> , which translates to a 37% reduction in processing cycles from state-of-art.

A Low-Latency and Area-Efficient Gram–Schmidt-Based QRD Architecture for MIMO Receiver

Despite a low algorithmic complexity, Gram–Schmidt (GS) method has not been widely employed in the dedicated hardware architecture of matrix decomposition due to its expensive square-root and division operations. This paper presents a low-latency and area-efficient QR decomposition (QRD) architecture based on the modified GS method. The low complexity architecture is enabled by efficiently substituting the square roots and divisions with coordinate rotation digital computer (CORDIC) operations. In the proposed architecture, when implementing the division by the results of square root, the key design point is that the rotation directions of CORDIC are shared between vectoring and rotation modes using the orthogonality of the CORDIC rotation matrix. As a result, the division operation can be performed with the assistance of square root, leading to the hardware cost reduction. The overhead of scaling factor compensation has also been reduced with pre-scaling. The proposed low complexity scheme can be implemented in the semipipelined and iterative architectures for high throughput and small area applications, respectively. Hardware implementation results with 65-nm CMOS process show that the proposed semipipelined architecture achieves 17% and 141% improvement of normalized hardware efficiency in QRD and projection operations, respectively, compared with the conventional approaches.

QR decomposition architecture using the iteration look‐ahead modified Gram–Schmidt algorithm

QR decomposition is extensively adopted in multiple-input–multiple-output orthogonal frequency-division multiplexing wireless communication systems, and is one of the performance bottlenecks in lots of high-performance wireless communication algorithms. To implement low processing latency QR decomposition with hardware, the authors propose a novel iterative look-ahead modified Gram–Schmidt (ILMGS) algorithm based on the traditional modified Gram–Schmidt (MGS) algorithm. They also design the corresponding triangular systolic array (TSA) architecture with the proposed ILMGS algorithm, which only needs n time slots for a n × n real matrix. For reducing the hardware overhead, they modify the TSA architecture into an iterative architecture. They also design a modified iterative architecture to further reduce the hardware overhead. The implementation results show that the normalised processing latency of the modified iterative architecture based on the proposed ILMGS algorithm is 1.36 times lower than the one based on the MGS algorithm. To the best of the authors’ knowledge, the designed architecture achieves the superior latency performance than the existing works.

Efficient implementation of iterative multi‐input–multi‐output orthogonal frequency‐division multiplexing receiver using minimum‐mean‐square error interference cancellation

An efficient hardware implementation scheme is proposed for iterative multi-input-multi-output orthogonal frequency-division multiplexing receiver which includes an MMSE-IC (minimum-mean-square error interference cancellation) detector, a channel estimator, a low-density parity-check (LDPC) decoder and other supporting modules. The proposed implementation uses the QR decomposition (QRD) of the complex-valued matrices with four coordinate rotation digital computer (CORDIC) cores and a back substitution to solve the MMSE-IC equations while the existing systolic array architectures require 15-38 CORDIC cores to achieve a similar throughput. The proposed 4-CORDIC QRD architecture can be configured as a 16-matrix or a 64-matrix pipelining by using a different number of multipliers combined with one-dimensional (1D) or 2D arrays of the back substitution, respectively. The channel estimator implements a commonly-used frequency domain least squares channel estimation with the canonic-signed-digits method, thanks to the character of the Zadroff-Chu sequence used as the pilot. In the LDPC decoder, the min-sum algorithm is implemented for the quasicyclic LDPC decoding. The two schemes for the MMSE-IC detector with different throughput and resource usages have been implemented in a Field Programmable Gate Array for a complete baseband turbo receiver. Their resource usages, throughputs and latencies are compared with the classic systolic array architectures, which demonstrate that the proposed receiver architecture achieves the best tradeoff between the throughput and the resource usage.

MIMO 검출기에 적용 가능한 저 복잡도 복합 QR 분해 구조

본 논문에서는 MIMO 검출기를 위한 저 복잡도 QR 분해 구조를 제시한다. 제안된 접근 방식에서는, QRD 하드웨어의 연산 복잡도를 감소시키기 위해 다양한 코딕 기반 QRD 알고리즘들이 효율적으로 조합된다. 다양한 QRD 알고리즘들에 대한 연산 복잡도 분석에 기초하여, QRD 과정의 매 단계마다 저 복잡도 접근 방식이 선택된다. 제안된 QRD 구조는 어떤 임의의 차원을 갖는 채널 매트릭스에도 적용 될 수 있고, 매트릭스 차원의 증가에 따라 연산 복잡도 감소도 늘어난다. 제안하는 QR 분해 하드웨어는 삼성 <TEX>$0.13{\mu}m$</TEX> 공정을 사용하여 구현되었다. 실험결과, <TEX>$4{\times}4$</TEX> 행렬의 QR 분해에 대한 제안 구조는 기존의 Householder 코딕 기반의 구조에 비해 47%의 QAR(QRD Rate/Gate count) 향상과 28%의 전력을 절감을 이뤄낼 수 있었다. This paper presents a low complexity QR decomposition (QRD) architecture for MIMO detector. In the proposed approach, various CORDIC-based QRD algorithms are efficiently combined together to reduce the computational complexity of the QRD hardware. Based on the computational complexity analysis on various QRD algorithms, a low complexity approach is selected at each stage of QRD process. The proposed QRD architecture can be applied to any arbitrary dimension of channel matrix, and the complexity reduction grows with the increasing matrix dimension. Our QR decomposition hardware was implemented using Samsung <TEX>$0.13{\mu}m$</TEX> technology. The numerical results show that the proposed architecture achieves 47% increase in the QAR (QRD Rate/Gate count) with 28.1% power savings over the conventional Householder CORDIC-based architecture for the <TEX>$4{\times}4$</TEX> matrix decomposition.

Sign-Select Lookahead CORDIC based High-Speed QR Decomposition Architecture for MIMO Receiver Applications

This paper presents a high-speed QR decomposition architecture for the multi-input-multi- output (MIMO) receiver based on Givens rotation. Under fast-varying channel, since the inverse matrix calculation has to be performed frequently in MIMO receiver, a high performance and low latency QR decomposition module is highly required. The proposed QR decomposition architecture is composed of Sign-Select Lookahead (SSL) coordinate rotation digital computer (CORDIC). In the SSL-CORDIC, the sign bits, which are computed ahead to select which direction to rotate, are used to select one of the last iteration results, therefore, the data dependencies on the previous iterations are efficiently removed. Our proposed QR decomposition module is implemented using TSMC 0.25 µm CMOS process. Experimental results show that the proposed QR architecture achieves 34.83% speed-up over the Compact CORDIC based architecture for the 4 × 4 matrix decomposition.