Push Architecture Research Articles

The push strategy of product design knowledge in cloud environment with the multidimensional hierarchical context and SSA-BPNN model

To assist designers in completing design tasks and improve the efficiency of product design, more and more design knowledge push approaches are coming about. With developments of information technology and cloud computing, knowledge service goes with the whole design process and it is represented by the knowledge push forming. The knowledge push is complex engineering, however, existing knowledge push approaches in traditional design patterns cannot exactly meet the personalized knowledge requirements of designers in cloud environment. To address this issue, we attempt to explore the push strategy of product design knowledge in cloud environment. Firstly, knowledge demands are analyzed with the multidimensional hierarchical context model and the design knowledge modeling is represented following characteristics of the cloud-based design pattern. Then, the knowledge push architecture contains the matching of knowledge to obtain alternative knowledge and the knowledge importance degree prediction with SSA-BPNN model to overcome the inaccuracy of judgments, which is put forward. Moreover, the push coefficient is calculated as the knowledge push reference. Eventually, an illustrative case of intelligent air conditioner product design in the cloud platform is taken to verify the application and performance of the proposed approach. We expect that this work could provide useful insights into the product design knowledge push in cloud environment.

A Low-Power 255-GHz Single-Stage Frequency Quadrupler in 130-nm SiGe BiCMOS

A frequency quadrupler for the up-conversion of a 63.75-GHz signal to an output frequency of 255 and 12.7 GHz of bandwidth for use in a local oscillator chain is presented. The presented circuit extends the common push–push architecture to a single-stage frequency quadrupler and improves upon existing designs concerning frequency of operation and conversion core efficiency. By replacing the usual $2\times 2$ architectures with the presented solution, the total dc power consumption can be reduced by over 75% with respect to state-of-the-art designs, while maintaining useful output power levels. To showcase the performance of the core, the design abstains from any buffers at the input or output. Consuming 22.4 mW the circuit produces −8.4 dBm of output power. Excluding the losses in the passive input network, the circuit achieves a conversion loss of 4.4 dB. The fundamental suppression is higher than 40 dB.

Design and implementation of a 94/188 GHz dual‐band VCO with gain‐enhanced frequency doubler IN 90 nm CMOS

ABSTRACTIn this work, a 94/188 GHz push–push voltage‐controlled oscillator (VCO) using gain‐enhanced frequency doubler is demonstrated in a 90 nm CMOS process. Compared with the traditional push–push architecture, the proposed one can significantly increase the second‐harmonic output signal due to the inductive series‐peaking gain‐enhancement of the full‐wave‐rectifier‐based frequency doubler. In addition, low power dissipation is achieved because the bias current of the frequency doubler is reused by the cross‐coupled transistors of the VCO. The VCO draws 12 mA current from a 1 V power supply, i.e. it only consumes 12 mW. At the fundamental port, the VCO achieves a tuning range of 92.6∼95 GHz and a low phase‐noise of −88.2 dBc/Hz at 1 MHz offset from the center frequency. The corresponding FOM is −177 dBc/Hz. At the push–push port, the VCO achieves a tuning range of 185.2∼190 GHz and a low phase‐noise of −82.5 dBc/Hz at 1 MHz offset from the center frequency. The corresponding FOM is −177.3 dBc/Hz. To the authors’ knowledge, the phase noise and FOM performances of the VCO are one of the best results ever reported for a W‐band or G‐band CMOS VCO. The circuit occupies a small chip area of 0.58 × 0.61 mm2, i.e. 0.35 mm2, excluding the test pads. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:675–681, 2017

Tolerating memory latency through push prefetching for pointer-intensive applications

Prefetching is often used to overlap memory latency with computation for array-based applications. However, prefetching for pointer-intensive applications remains a challenge because of the irregular memory access pattern and pointer-chasing problem. In this paper, we proposed a cooperative hardware/software prefetching framework, the push architecture, which is designed specifically for linked data structures. The push architecture exploits program structure for future address generation instead of relying on past address history. It identifies the load instructions that traverse a LDS and uses a prefetch engine to execute them ahead of the CPU execution. This allows the prefetch engine to successfully generate future addresses. To overcome the serial nature of LDS address generation, the push architecture employs a novel data movement model. It attaches the prefetch engine to each level of the memory hierarchy and pushes , rather than pulls , data to the CPU. This push model decouples the pointer dereference from the transfer of the current node up to the processor. Thus a series of pointer dereferences becomes a pipelined process rather than a serial process. Simulation results show that the push architecture can reduce up to 100% of memory stall time on a suite of pointer-intensive applications, reducing overall execution time by an average 15%.

Staggered push - a linearly scalable architecture for push-based parallel video servers

With the rapid performance improvements in low-cost PCs, it becomes increasingly practical and cost-effective to implement large-scale video-on-demand (VoD) systems around parallel PC servers. This paper proposes a novel parallel video server architecture where video data are striped across an array of autonomous servers connected by an interconnection network. To coordinate data transmissions from multiple autonomous servers to a client station, a staggered push scheduling algorithm is proposed. A system model is constructed to quantify the performance of the architecture. Unlike most studies, this work does not assume the existence of a global clock among the servers and tackles two problems arising from server asynchrony: inconsistent schedule assignment and traffic overlapping. The former problem is solved by using an admission scheduler and the latter problem is solved by an over-rate transmission scheme. Analytical results prove a remarkable property of the staggered push architecture: as long as the network has sufficient capacity, the system can be scaled up linearly to an arbitrary number of servers. Design examples and numerical results are used to evaluate the proposed architecture under realistic assumptions and to compare it against other architecture.

Supporting server-level fault tolerance in concurrent-push-based parallel video servers

Parallel video servers have been proposed for building large-scale video-on-demand (VoD) systems from multiple low-cost servers. However, when adding more servers to scale up the capacity, system-level reliability will decrease as failure of any one of the servers will cripple the entire system. To tackle this reliability problem, this paper proposes and analyzes architectures to support server-level fault tolerance in parallel video servers. Based on the concurrent push architecture proposed earlier, this paper tackles three problems pertaining to fault tolerance, namely redundancy management, redundant data transmission protocol, and real-time fault masking. First, redundant data based on erasure codes are introduced to video data stored in the servers, which are then delivered to the clients to support fault tolerance. Despite the success of distributed redundancy striping schemes such as RAID-5 in disk array implementations, we discover that similar schemes extended to the server context do not scale well. Instead, we propose a redundant server scheme that is both scalable, and with lower total server buffer requirement. Second, two protocols are proposed to manage the transmission of redundant data to the clients, namely forward erasure correction which always transmits redundant data, and on-demand correction which transmits redundant data only after a server failure is detected. Third, to enable ongoing video sessions to maintain nonstop video playback during failure, we propose using fault masking at the client to recompute lost video data in real-time. In particular we derive the amount of client buffer required so that nonstop, continuous video playback can be maintained despite server failures.

The CMS event builder demonstrator based on Myrinet

The data acquisition system for the CMS experiment at the Large Hadron Collider (LHC) will require a large and high performance event building network. Several switch technologies are currently being evaluated in order to compare different architectures for the event builder. One candidate is Myrinet. This paper describes the demonstrator which has been set up to study a small-scale (8/spl times/8) event builder based on a Myrinet switch. Measurements are presented on throughput, overhead and scaling for various traffic conditions. Results are shown on event building with a push architecture.

Multi-level texture caching for 3D graphics hardware

Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval of texture during rasterization, and the application is responsible for managing this memory. The push architecture has a bandwidth advantage, but disadvantages of limited texture capacity, escalation of accelerator memory requirements (and therefore cost), and poor memory utilization. The push architecture also requires the programmer to solve the bin- packing problem of managing accelerator memory each frame. More recently graphics hardware on PC-class machines has moved to an implementation of what we call the pull architecture. Texture is stored in system memory and downloaded by the accelerator as needed. The pull architecture has advantages of texture capacity, stems the escalation of accelerator memory requirements, and has good memory utilization. It also frees the programmer from accelerator texture memory management. However, the pull architecture suffers escalating requirements for bandwidth from main memory to the accelerator. In this paper we propose multi-level texture caching to provide the accelerator with the bandwidth advantages of the push architecture combined with the capacity advantages of the pull architecture. We have studied the feasibility of 2-level caching and found the following: (1) significant re-use of texture between frames; (2) L2 caching requires significantly less memory than the push architecture; (3) L2 caching requires significantly less bandwidth from host memory than the pull architecture; (4) L2 caching enables implementation of smaller L1 caches that would otherwise bandwidth-limit accelerators on the workloads in this paper. Results suggest that an L2 cache achieves the original advantage of the pull architecture --- stemming the growth of local texture memory --- while at the same time stemming the current explosion in demand for texture bandwidth between host memory and the accelerator.