Pulse Width Modulation Technique Research Articles

Improve the voltage profile of the grid-integrated induction motor with a fuzzy-based voltage source converter

This article suggests installing a series compensator on grid-connected induction motors that allows for the ride-through of unbalanced voltage sag. Fuzzy logic controls the motor voltages in a standard three-phase voltage source inverter or voltage source inverter (VSI). An open-ended three-phase machine and the grid form a series connection for the VSI. The proposed system is well suited for uses where frequency variation is unnecessary, such as with large pumps or fans. There is no requirement for a direct current (DC) source or injection transformer when conducting an electric mutual coupling The severity of the sag in the grid voltage that will prevent EMC from shutting down is proportional to the load on the motors. An increase in the voltage of the DC link may be necessary if the voltage is not balanced. A 1.5 hp four-pole induction motor was used alongside grid voltage disturbances to test the proposed compensator's ride-through capability. Grid's current analysis demonstrates that the proposed system does not require the addition of a passive filter to achieve low levels of total harmonic distortion (THD). Additionally, the control strategy, component ratings, and analysis of the converter's output voltage operating principle and pulse width modulation technique are covered. The system's viability is shown via simulation and experimental results.

Performance analysis for induction motor fed by reduced switch symmetrical multilevel inverter topology

Due to its capacity to supply more voltage levels than conventional 2-level inverters, multilevel inverters have attracted a lot of attention in recent years. Multilevel inverters may produce output waveforms that nearly approximate sinusoidal waveforms because to this characteristic, which also significantly lowers harmonic distortion. In many different power conversion systems, the introduction of reduced switch symmetrical multilevel inverter topologies has drawn significant interest. Numerous benefits, such as higher output voltage quality, reduced harmonic distortions, and increased power conversion efficiency, are provided by these novel topologies. The inclusion of these inverters in the feeding of induction motors is one of their many prominent uses. In this paper, a generalized topology is presented that generates nine levels using nine switching devices. To reduce complexity, switching pulses are generated using a low frequency pulse width modulation technique. MATLAB/Simulink is used to analyze the performance assessment of a unique three-phase symmetric cascaded multilevel inverter-based reduced switch symmetrical inverter fed induction motor drive, brushless DC (BLDC) motor and grid has been verified. According to the findings the total harmonic distortion (THD) is found to be 15% for a three-phase system and as the number of levels increases to 17 level the THD is 7.10%.

Solar PV based seventeen level reduced switch symmetrical multilevel inverter topology fed induction motor

Multilevel inverters have received a lot of interest in recent years due to their ability to deliver more voltage levels than typical two-level inverters. Because of this property, multilevel inverters can produce output waveforms that closely resemble sinusoidal waveforms, lowering harmonic distortion dramatically. The emergence of reduced switch symmetrical multilevel inverter topologies has developed the curiosity of many different power conversion systems. These new topologies offer numerous advantages, including greater output voltage quality, fewer harmonic distortions, and increased power conversion efficiency. The inclusion of these inverters in the feeding of induction motors is one of their many prominent uses. A 17 levels of multi-level inverter (MLI) topology is presented with reduced switch count and harmonic reduction for power quality improvement. The inverter is fed by isolated equal photovoltaic panels which act as direct current or DC source. To reduce complexity, switching pulses are generated using hybrid pulse width modulation technique which is designed as controller. Through the use of MATLAB/Simulink, the performance assessment of a unique cascaded multilevel inverter-based reduced switch symmetrical inverter feeding an induction motor drive has been verified. The harmonic distortion with reduced switches obtained is 7.47% which is comparatively less than when compared with conventional cascaded H-bridge topology.

Multicarrier PWM techniques for three phase modular multilevel converter application in MRI systems

This research paper presents about the performance analysis of three phase modular multilevel converter with level shifted (phase disposition pulse width modulation) and phase shifted pulse width modulation (PWM) method. This research not only discusses the significance of different modulation procedures in the context of modular multilevel converters but also carefully evaluates each of their unique performance characteristics. This research is based on the fundamental creation of pulses and patterns that can only be acquired by comparing sinusoidal reference signals with triangular carrier signal. Both levels shifted (phase disposition) and phase shifted PWM procedures are used to calculate the phase output voltage of a converter at 2N+1 level. The output waveform is crucially shaped by these modulation techniques, which also ensure effective energy conversion and lower harmonic content. On the basis of the output voltage waveform's quality, the comparative research is conducted and simulated results were presented.

Photoluminescence measurement of ruby excited by duty ratio-controlled pulse light-emitting diodes (LED) light source.

Photoluminescence (PL) spectra from ruby were obtained using a highly stable LED light source, employing pulse width modulation technique for excitation. The temporal variation in PL intensity caused by the increasing temperature of the LED used for excitation can be mitigated by adjusting the duty ratio (%) of the pulsed LED light to below 10% for cooling the LED. Stable PL spectra measurements were achieved with a duty ratio of less than 10% using a duty ratio-controlled pulsed LED light source, as temperature fluctuations in LED light intensity are minimized at duty ratios less than 10%. Furthermore, fluctuations in the measured PL intensity were diminished by setting the frequency of the pulsed LED light source to greater than 1kHz. This method enables more reliable, cost-effective, and stable PL measurements for material characterization in semiconductors, photonics, and nanotechnology.

Multilevel inverter: harmonic analysis with and without filters for RL load using SPWM techniques

Multilevel inverter (MLI) gains more attraction compared to conventional inverter as it generates a staircase output voltage that mimics sine waves of desired output voltage. Cascaded H-bridge (CHB) topology is taken into consideration owing to several benefits over conventional inverters. Various levels of CHB (3 and 5 level) inverters are compared on diverse parameters. In this paper level shift sinusoidal pulse width modulation technique is considered resulting in reduced lower order harmonic (LOH) distortion and improve the quality of output current and voltage depending on the load. Since, the LOH are too dangerous for power electronic circuits. An attempt to shift all the LOH above 50th order depending on the modulation technique with analogy for selecting an appropriate switching frequency is highlighted. The effect of change in switching frequency and modulation index (MI) on RMS output voltage, % voltage total harmonic distortion (VTHD), output power factor with different modulation techniques such as phase disposition pulse width modulation (PsD PWM), phase opposite disposition (POD PWM), alternative phase opposition disposition (APOD PWM) is portrayed in the paper. Further, to boost the performance a unique filter circuits with optimal design values of Inductance and capacitance driven with IEEE 519-2022 standards. The effectiveness in terms of with and without filter is verified and validated using MATLAB.

Power quality improvement of PWM AC Chopper fed capacitor run induction motor using BFO, PSO and CSO Algorithm

This paper exhibits performance enhancement of PWM AC chopper fed capacitor run induction motor by using optimization algorithm. The PWM AC chopper utilizes enhanced asymmetrical pulse width modulation technique by incorporating four pulses in quarter cycle. The switching instants are obtained optimally by bacteria foraging optimization, particle swarm optimization and cuckoo search optimization algorithm. The power quality parameters considered in this paper are total harmonic distortion of current, total harmonic distortion of voltage, power factor and efficiency. The simulation result shows that proposed algorithm shows better performance compared to other optimization techniques.

An FPGA-based balancing of capacitor voltage for multi-level inverter

ABSTRACT This paper introduces a novel cascaded multilevel inverter circuit configuration aimed at generating a five-level load voltage using a single DC source and a capacitor. In this inverter configuration, an additional switch is added to the charging circuit which helps to charge the capacitor from the DC source. Additionally, an inductor is incorporated to mitigate the substantial charging current during capacitor charging operation. A level-shifted pulse width modulation (LS-PWM) technique is implemented to generate gate pulses for both inverter and charging switches. The capacitor gets charged when an extra switch is enabled and discharged when it is connected to a load. Analysis of charging and discharging of capacitor is described thoroughly in this paper. Each operational mode of the inverter is thoroughly analysed. Furthermore, the proposed five-level inverter setup is designed, and its control logic is implemented using FPGA platform. Subsequently, simulation and experimental investigations are conducted under varied loads and different modulation indices to evaluate the efficacy of the proposed inverter configuration and the respective results are presented.

A new single modulating and single carrier signal based control technique for symmetrical and asymmetrical multilevel inverter topology

Abstract In literature, to generate gate pulses for any inverter topology, most of the authors are using a single modulating signal with (level-1) or (level-1)/2 carrier-based pulse width modulation (PWM) techniques and single carrier (SC) signal with (level-1)/2 modulating signal based PWM techniques. Then, while going to higher-level inverter topologies, the complexity of the PWM control approach in both cases can increase. To reduce the control complexity, few authors have reported a single modulating signal with single carrier-based PWM techniques. However, these techniques need more mathematical equations and if-else loops. This article proposes a new single-modulating and single-carrier signal-based generalized PWM control approach using floor function (FF). This technique has been verified by considering one of the single-phase conventional symmetrical and asymmetrical multilevel inverter (MLI) topologies. Generally, FF rounds the value to the nearest integer towards the negative infinity. The proposed PWM control implementation process is very simple and suitable for both high switching frequency (HSF) and low switching frequency (LSF) operations. The proposed control technique (PCT) has been experimentally verified with different steady-state and transient-state studies of results under standalone operation.

Performance Characteristics of a Newly Developed Asymmetric Seven-Level Inverter Utilizing Various Hybrid Pulse Width Modulation Strategies

This study unveils a notable breakthrough in inverter technology, holding promise for substantial improvements in voltage quality and the attenuation of harmonic distortions within power systems. This study concentrates on the design and implementation of a novel Seven-Level Asymmetric Inverter (NSLAI) by incorporating various hybrid Pulse Width Modulation (PWM) techniques. The primary goal is to improve the output voltage magnitude while decreasing the Total harmonics compared to conventional PWM methods. The investigation introduces a novel Seven-Level Asymmetric Inverter (NSLAI) with innovative Hybrid Pulse Width Modulation (PWM) strategy. The purpose of this study is to investigate the distinct features of a recently developed asymmetric seven-level inverter, with a focus on exploring its characteristics through the implementation of diverse hybrid pulse width modulation strategies. Hybrid PWM methodology intricately centers on enhancing voltage quality and achieving better harmonious spectral characteristics. The gate signal producing approach for this suggested PWM technology incorporates a hybrid PWM methodology that combines trapezoidal and sinusoidal waveforms, as well as a standard triangular carrier signal enabling NSLAI. The hybrid version of PWM practices is deliberately used to generate switching signals for the NSLAI. An intensive evaluation of numerous indicators of effectiveness across multiple modulation indexes leads in the demonstrating of quantitative findings that compare the unique Hybrid PWM practice with established PWM tactics. Notably, the hybrid reference Carrier Overlapping strategy has emerged as a leading approach surpassing conventional pulse width modulation techniques. It achieves a significantly higher fundamental Root Mean Square voltage output and remarkably lower percentage of Total Harmonic Distortion values compared to all within the hybrid reference Variable Frequency strategy. The principal analytical tool used in the modeling investigation is MATLAB-SIMULINK. This study marks a watershed moment in the development of inverters, claiming significant improvements in battery power quality and distortion caused by harmonics avoidance across power systems, as evidenced by extensive simulation and prototype-based discoveries.

Harmonizing power systems with a 13-level modified Packed U-Cells multi-level inverter: Design and implementation

Traditional multilevel inverter designs often face complexity challenges, prompting the need for a simplified solution. This study introduces and evaluates the performance of a Modified Packed U-Cells (MPUC) inverter in the realm of multilevel inverter technology. The study addresses challenges associated with conventional multilevel inverters and proposes the MPUC inverter as a solution to simplify the design complexity. The MPUC inverter, utilizing three DC sources and eight switches, presents a groundbreaking thirteen-level output waveform. The primary focus lies in assessing the inverter's performance in terms of Total Harmonic Distortion (THD) and output voltage. Utilizing MATLAB/Simulink, the inverter's performance is evaluated with and without Pulse Width Modulation (PWM) strategies. The results reveal a notable reduction in THD, from 26.25% to 9.91% post-filtering when PWM is not employed. Various multi-carrier Level-Shifted PWM strategies, including PDPWM, PODPWM, APODPWM, and COPWM, are explored to enhance output waveform smoothness and efficiency. Unequal Carrier strategies, specifically UEAPDPWM and UEAPODPWM, emerge as superior in THD management at different frequency ranges. The study further incorporates real-time hardware implementation of the proposed 13-level MPUC topology, highlighting the success of the UEAPD-PWM strategy in improving waveform quality. The research aims to establish a multilevel inverter design protocol meeting international standards and emphasizes the pivotal role of PWM techniques in enhancing waveform quality. This comprehensive evaluation contributes to advancing the field of multilevel inverter technology and sets a benchmark for future research in this domain.

Real-time of a two-level three-phase inverter controlled by PWM and full wave techniques

Sustainability in power generation is readily available and must be able to adapt to a variety of energy needs or integrate seamlessly into alternative distribution networks. This research aims to bridge the gap between continuous energy production and efficient energy utilization by advancing the understanding and application of three-phase dual-level voltage inverters. This study focuses on two main objectives: firstly, to develop a comprehensive model and secondly, to validate the functionality of a three-phase two-level voltage inverter. The control strategy employed for this inverter involves the full-wave method and pulse-width modulation (PWM). The results obtained from the hardware implementation of these control methods show impressive levels of success, closely matching the expected performance of the three-phase inverter. This success underlines the robustness and effectiveness of both full-wave and PWM control strategies. To further underline their practical applicability, experimental validation of PWM and Full Wave control methods is demonstrated in a controlled research laboratory environment.

PROGRESSIVE STEP MAXIMUM POWER TRACKER FOR CASCADED INVERTER INDUCTION MOTOR DRIVE

This paper presents the idea of an isolated photovoltaic (PV) based cascaded two-level inverter (CTLI), driving squirrel cage induction motor (SCIM). The connected non-linear load approximately represents a centrifugal pump. The control system of this drive is based on a motor control system along with a progressive step perturb and observe (PSPnO) maximum power point tracking (MPPT) technique for the PV sources towards better utilization of the source. This PSPnO MPPT system intends to operate the SCIM so that the energy developed by PV is utilized entirely through variation of the dc-link voltages of the CTLI under both uncertain variances of non-linear load torque and unpredictable solar irradiance. This PSPnO MPPT algorithm has been engaged in the control scheme for generating reference dc-link voltage. This motor control system is designed to operate in a rotor-flux-oriented rotating reference frame. As for generating CTLI’s switching pulses, the space vector pulse width modulation (SVPWM) technique has been used for its good dynamic response. The whole system is designed to be deployable on a low-computation device. The simulations conducted by Simulink and the results are furnished considering various operational conditions.

Monolithic design of self-adaptive CMOS converter and robust event-triggered consensus control for integration of multi-renewable energy sources with battery storage system

Recently, integrating renewable energy sources (RESs) has been one of the most effective ways to overcome the power shortage problems due to the cumulative load demand, which cannot be covered using conventional power production. DC-DC converters with a wide voltage conversion range are highly important when integrating RESs to achieve voltage matching. In recent years, many large-scale improvements have been made to the DC-DC converters to improve reliability, effectiveness, flexibility, modularity, and cost-effectiveness. This study investigates the feasibility of integrating RESs and designing the most effective structure using complementary metal-oxide semiconductors (CMOS) for DC-DC converters. A novel monolithic CMOS buck converter with an adaptive sensing feedback system (ASFS) circuit is proposed for renewable integrated systems. The proposed converter based on ASFS provides a wide range of conversion voltages, low cost, and reliability. It depends on the pulse-width modulation (PWM) technique with a voltage-control duty-cycle (VCDC) circuit. The proposed multi-input DC-DC converter is tested to integrate three RESs to form an integrated hybrid system. The proposed converter is built to integrate the PV, wind turbine (WT), wave energy source, and battery energy storage system (BESS). The proposed DC-DC converter is tested to adjust the output voltage of the RESs at 12 V with a load current of 2.4 A to facilitate the integration process. The results show the success of the proposed converter in maintaining the output voltage at 12 V, with maximum efficiency of the CMOS buck DC-DC converter reaching 96.25 % over a wide input voltage range from 15 V to 35 V. Moreover, the maximum peak-peak ripple over the output voltage reaches 600 mV at the maximum input voltage of 35 V. A control method-based event-triggered consensus algorithm has been proposed to regulate the system voltage and ensure active power sharing in the microgrid system. The controller's settling time and rise time have been measured, and a robustness analysis has been performed based on the connections and disconnections of DGs and the impact of faults.

Multilevel Inverter with Enhanced THD Value used in Grid Connected Applications

In this work, the relationships among pulse width modulation (PWM), sinusoidal pulse width modulation (SPWM), and space-vector pulse width modulation (SVPWM) for three-phase inverters will be analyzed to better comprehend their differences. detailed comparison of the three modulation schemes under study’s Total Harmonic Distortion (THD). High-power applications are increasingly concentrating on converter technology. This growing importance may be attributed to its improved output waveforms over the 3- carrier-based sinusoidal pulse width modulation (SPWM). To control and modulate multi-level inverters, many techniques are employed. These methods are categorized based on how frequently they switch. The ripple current rating, capacitance value, and voltage balance in the DC bus capacitors are all impacted by the pulse width modulation techniques. It is crucial to select the modulation method based on the current control requirements, as this determines the output voltage waveform’s harmonic content. SVPWM is gradually becoming more and more popular in industries because of its improved dc bus utilization and ease of digital realization. This work examines PWM, Sinusoidal, and SVPWM feeding a load connected to RL. Three different methodologies’ performances are compared as these methods are investigated through simulation with MATLAB/SIMULINK software.

Efficient water-related failure detection in PEM fuel cells: Combining a PEMFCs fractional order impedance model with FFT-PWM techniques and artificial neural network classification

Water management and early detection of faults in proton exchange membrane fuel cells (PEMFCs) are among the most critical constraints that limit the optimal spread of this type of energy. Consequently, it is necessary to enhance the reliability and durability of PEMFCs by developing an approach to diagnose and identify water failure modes. This paper proposes an effective and simple method to detect, diagnose, and classify various water failure modes in PEMFCs using a hybrid diagnostic approach. This approach combines the PEMFC fractional order impedance model (FOIM) with fast Fourier transform pulse width modulation (FFT-PWM) techniques and artificial neural network pattern recognition (ANN-PR) classification. The results show an accurate match between the electrochemical impedance spectroscopy (EIS) experimental data, the Nyquist impedance spectra of FOIM, and the FFT-PWM algorithm as a proposed alternative technique to EIS measurements. Learning of ANN-PR was performed using the frequency spectrum amplitude (FSA) database of the voltage and current signals produced by the PEMFCs FOIM DC/DC boost converter, which was generated using the FFT-PWM algorithm. The ANN-PR achieved low values for error accuracy, with the Low Square Error and Learning Error reaching 6.676 × 10−19 and 1.888 × 10−16, respectively. The elements inside the confusion matrix and the rest of the matrices confirm that the proposed model's accuracy, precision, recall, and high F1 score reached 100%. Furthermore, all predictions made by the ANN-PR model were consistently accurate across all areas of failure detection. Overall, the proposed method helps in analyzing, diagnosing, and classifying fuel cell failure modes such as flooding and drying, which may simplify the health assessment of PEMFC.

A new class of active impedance source inverter with low voltage stress on semiconductors

SummaryIn this paper, a new group of active impedance source inverters, along with a suitable control method based on the pulse width modulation (PWM) technique, is presented. The purpose of these inverters is to reduce the voltage stress on capacitors, diodes, and switches compared to other topologies. Using the proposed control method to produce the gate pulse of the switches, all operating modes of one of the proposed inverters, in two different operations (synchrony and asynchrony), to calculate boost factor and critical inductance in the boundary condition, are analyzed. Furthermore, all equations of voltage and current of components to design the suitable amounts of capacitors and inductors are calculated. Then, the comparative analysis from different points of view, such as boost factor, total voltage blocked by diodes and switches, and voltage stresses on capacitors between the proposed topology and conventional structures to examine the advantages and disadvantages, is done. Also, the losses and efficiency of the proposed topology at different loads are fully given. Finally, a prototype of the proposed topology is designed, and its experimental results are provided to check the performance and correctness of the obtained equations in different operating modes.

A Wireless Potentiostat Exploiting PWM-DAC for Interfacing of Wearable Electrochemical Biosensors in Non-Invasive Monitoring of Glucose Level

In this paper, a wireless potentiostat code-named ElectroSense, for interfacing of wearable electrochemical biosensors, will be presented. The system is devoted to non-invasive monitoring of glucose in wearable medical applications. Differently from other potentiostats in literature, which use digital-to-analog converters (DACs) as discrete components or integrated in high-end microcontrollers, in this work the pulse width modulation (PWM) technique is exploited through PWM-DAC approach to generate signals. The ubiquitous presence of integrated PWM peripherals in low-end microcontrollers, which generally also integrate analog-to-digital converters (ADCs), enables both the generation and acquisition of read-out signals on a single cheap electronic device without additional hardware. By this way, system’s production costs, power consumption, and system’s size are greatly reduced with respect to other solutions. All these features allow the system’s adoption in wearable healthcare Internet-of-things (IoT) ecosystems. A description of both the sensing technology and the circuit will be discussed in detail, emphasizing advantages and drawbacks of the PWM-DAC approach. Experimental measurements will prove the efficacy of the proposed electronic system for non-invasive monitoring of glucose in wearable medical applications.

Simulation and FPGA based Implementation of PI and Fuzzy Controllers for Cascaded Asymmetric Multilevel Inverter

The main objective of this work is to improve the performance of Multilevel Inverter by using the novel LS-PD- PWM and controlling technique instead of the existing approach. The proposed work focus on closed loop controller such as existing PI and Fuzzy Logic Controller for resistive load with Multilevel Inverter. The proposed Asymmetric fifteen level Inverter offers less THD and high frequency than the Asymmetric nine level inverter. Asymmetric multilevel inverter is used to reduce the switching losses and THD. In this work is the generation and implementation of Pulse Width Modulation (PWM) techniques using Field Programmable Gate Array (FPGA) for Multilevel Inverter. PWM can be generated via Microprocessors, Microcontroller, FPGA and DSP Processors. Higher density Programmable Logic Devices (PLD) such as FPGAs can be used to amalgamate large amounts of logic into a single Integrated. Pulse width modulation (PWM) is generally used in power converter control. To generate LS-PD- PWM by using FPGA, this occupies less memory capacity and accurate than conventional one. An efficient PWM generation technique is performed using FPGA for lower frequency applications. Simulation and synthesis is done by ModelSim6.3c and Xilinx10.1. Further, the Implementation is carried out by FPGA Spartan3 Xc3s50. Key Word: PWM, FPGA, PLD (Programmable Logic Devices), LS-PD-PWM

Asymmetrical multi‐level inverter by using space vector pulse width modulation technique for low and medium power applications

SummaryA DC to AC converter is developed in this paper. This proposes a single‐phase five‐level inverter is developed in such a way that one DC source is used. The structure of the inverter is modular and the capacitor has self‐voltage balancing capability, which eliminates the need for sensors or an additional control loop. This paper presents the schematic diagram of the proposed topology, principle of operation, and the concepts of sinusoidal pulse width modulation (SPWM) for single‐phase and space vector pulse width modulation (SVPWM) for three‐phase. To further prove the advantage, power loss, and parameter computations are calculated mathematically. Low‐voltage stress is achieved in the proposed topology because the blocking voltages of all the switches are constrained to the input voltage. A comparison table is presented between SPWM and SVPWM schemes in three‐phase inverter. The proposed asymmetrical five‐level configuration setup is constructed, and experiments are performed inside the laboratory. The controller of the converter has been implemented in the field‐programmable gate array (FPGA) platform. In order to confirm the viability of the suggested topology, experimental results are provided for single‐phase arrangement. By using the FPGA platform, real‐time implementation is done for a three‐phase inverter topology.