Pseudorandom Bit Stream Research Articles

SBS suppression using PRBS phase modulation with different orders.

The Brillouin instability (BI) caused by stimulated Brillouin scattering (SBS) can limit the output power of high-energy laser amplifiers. Pseudo-random bitstream (PRBS) phase modulation is an effective modulation technique to suppress BI. In this paper, we study the impact of the PRBS order and modulation frequency on the BI threshold for different Brillouin linewidths. PRBS phase modulation with a higher order will break the power into a larger number of frequency tones with a lower maximum power in each tone, leading to a higher BI threshold and a smaller tone spacing. However, the BI threshold may saturate when the tone spacing in the power spectra approaches the Brillouin linewidth. For a given Brillouin linewidth, our results allow us to determine the order of PRBS beyond which there is no further improvement in the threshold. When a specific threshold power is desired, the minimum PRBS order required decreases as the Brillouin linewidth increases. When the PRBS order is too large, the BI threshold deteriorates, and this deterioration occurs at smaller PRBS orders as the Brillouin linewidth increases. We investigate the dependence of the optimal PRBS order on the averaging time and fiber length, and we did not find a significant dependence. We also derive a simple equation that relates the BI threshold for different PRBS orders. Hence, the increase in BI threshold using an arbitrary order PRBS phase modulation may be predicted using the BI threshold from a lower PRBS order, which is computationally less time-consuming to compute.

High-Spatial-Resolution Brillouin Optical Correlation Domain Analysis Using Short-Pulse Optical Sources

High-spatial-resolution distributed optical fiber sensing based on Brillouin optical correlation domain analysis (BOCDA) using short-pulse optical sources is demonstrated. Short optical pulses phase-modulated with a pseudo random bit stream (PRBS) are used for pump and Stokes probe lights for the correlation-domain measurement of distributions of local Brillouin frequency shift (BFS). Because the excitation of acoustic wave is tightly confined in short length along the fiber owing to the short pulse duration, spatial resolution of the measurement is improved as compared with the case using not-return-to-zero pulses. In this experiment, BFS variation in a 2 mm standard single-mode fiber section is clearly detected by the use of an external cavity mode-locked semiconductor laser emitting 3 ps pulses as the light source. Spatial resolution shorter than 1 mm is obtained. Scanning of measurement location is achieved electrically by changing the clock speed of the PRBS, which is an advantage of the proposed scheme over the high-spatial-resolution BOCDA using amplified spontaneous emission as a light source. Theoretical estimation of Brillouin gain that the short-pulse Stokes probe light acquires is presented.

Power delivery network impedance characterization for high speed I/O interfaces using PRBS transmissions

This paper presents a method to characterize power delivery network impedance seen at the silicon level in a high-speed I/O interface using pseudorandom bit stream (PRBS) patterns. Moreover, results from a transient simulation using the extracted impedance are compared with laboratory measurements, showing good correlation.

STRAUSS: Spectral Transform Use in Stochastic Circuit Synthesis

1 Stochastic computing (SC) is an approximate computing technique that processes data in the form of long pseudorandom bit-streams which can be interpreted as probabilities. Its key advantages are low-complexity hardware and high-error tolerance. SC has recently been finding application in several important areas, including image processing, artificial neural networks, and low-density parity check decoding. Despite a long history, SC still lacks a comprehensive design methodology, so existing designs tend to be either ad hoc or based on specialized design methods. In this paper, we demonstrate a fundamental relation between stochastic circuits and spectral transforms. Based on this, we propose a general, transform-based approach to the analysis and synthesis of SC circuits. We implemented this approach in a program spectral transform use in stochastic circuit synthesis (STRAUSS), which also includes a method of optimizing stochastic number-generation circuitry. Finally, we show that the area cost of the circuits generated by STRAUSS is significantly smaller than that of previous work. 1 Parts of this paper are based on “A spectral transform approach to stochastic circuits,” which was presented at the International Conference on Computer Design, Oct. 2012 [3] .

Simple ultrafast all-optical AND logic gate

A simple scheme for an all-optical AND logic gate is proposed based on a sagnac interferometric structure. The operations of this scheme with a 40-Gbit/s return-to-zero (RZ) pseudorandom bit stream (PRBS) are simulated correctly with an output extinction ratio (ER) of about 14.7 dB. Through numerical analyses and discussions, it can be seen that the output ER of the AND operation is improved more than 6 dB, and the output pattern effect is decreased by about 0.4, compared to terahertz optical asymmetric demultiplexer schemes under the same condition. Furthermore, the carrier recovery time of a semiconductor optical amplifier (SOA) is no longer a crucial parameter to restrict the operation speed of this scheme. This scheme is potentially capable of AND operation rates to 100 Gbit/s.

A Power-Efficient Clock and Data Recovery Circuit in 0.18 $\mu{\hbox {m}}$ CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 mum CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of 0.045 mm2 /channel, with the total aggregate data bit rate of 20 Gb/s. The measured FTOL is plusmn3.5% and no error was detected for a 231-1 pseudo-random bit stream (PRBS) input data for 30 minutes, meaning that the bit error rate (BER) is smaller than 10-12. Meanwhile, a shared-PLL (phase-locked loop) with a wide tuning range and compensated loop gain has been introduced to tune the center frequency of all CDR channels to the desired value.

A 50-Gbit/s 450-mW Full-Rate 4:1 Multiplexer With Multiphase Clock Architecture in 0.13-$\mu{\hbox {m}}$ InP HEMT Technology

A full-rate multiplexer (MUX) with a multiphase clock architecture for over 40 Gbit/s optical communication systems is presented. The 4:1 MUX is comprised of a re-timer based on a D-type flip-flop (DFF) and a clock tree system that uses EXOR-type delay buffers to match its skews well to those of the data. The supply voltage is reduced to -1.5 V by analyzing the voltage allocation. Fabricated in a 0.13-mum InP HEMT technology, a DFF test circuit achieved 75-Gbit/s operation and exhibited performance sufficient to re-time 50-Gbit/s serialized data. The 4:1 MUX measurement results demonstrate successful 50-Gbit/s operation at room temperature, and 40-Gbit/s operation, which has 10-11 error free for 231 - 1 pseudorandom bit stream (PRBS) data, up to an ambient temperature of 90 degrees or down to - 1.24 V of supply voltage. The circuit consumes 450 mW at a - 1.5-V supply and exhibits an output jitter of 283 fs rms at 50-Gbit/s operation. We also propose a multiphase clock generator for a MUX that has a serialization of more than four channels.

A 24-Gsps 3-Bit Nyquist ADC Using InP HBTs for DSP-Based Electronic Dispersion Compensation

A 3-bit flash analog-to-digital converter (ADC) for electronic dispersion compensation (EDC) was developed using InP HBTs. Nyquist operation was confirmed up to 24 Gsps, which enables oversampling acquisition for 10 Gbit/s non-return-to-zero (NRZ) signals. The ADC can also be operated at up to 37 Gsps for low input frequencies. To reduce aperture jitter and achieve a wide band of over 7 GHz, an analog input signal for all pre-amplifiers and a clock signal for all latched comparators are provided as traveling waves through coplanar transmission lines. EDC was demonstrated by capturing a 10-Gbit/s pseudo-random bit stream (PRBS) with the waveform degraded by polarization-mode dispersion (PMD). By using the captured data, we confirmed that a calculation of a transversal filter mitigates PMD.

10 ps pulse all-optical discrimination using a high-speedsaturable absorber optical gate

The authors propose a novel all-optical signal discriminator (ODSC) using a high-speed saturable absorber optical gate which has >20 dB extinction ratio and threshold response. Error-free all-optical discrimination is realised for 10 ps optical pulses encoded by a 622 Mbit/s PRBS (pseudorandom bit stream).