Proximity Effect Correction System Research Articles

High-performance proximity effect correction for sub-70 nm design rule system on chip devices in 100 kV electron projection lithography

The proximity effect correction (PEC) system to achieve the practical processing time and data volume for sub-65 nm design-rule system on chip (SoC) devices is improved. The lump method, which is the technique to process several subfields at a time, is used to reduce the processing time for PEC. The hierarchical data processing for PEC is also proposed to reduce the data volume. A PC cluster system has been used to reduce the processing time for PEC. For an actual 70 nm design-rule SoC device data, the processing time has been reduced from 7.8 h to 10.3 min and the data volume has been reduced from 12.4 to 2.6 GB by using the lump method, the hierarchical data processing, and a ten PC cluster system. And, we have confirmed that the required critical dimension accuracy of ±5% is achieved for the device data in the simulation. We have successfully fabricated a full-size 8 in. Si stencil mask using the data with our PEC system for an actual 70 nm design-rule SoC device.

High-Speed Proximity Effect Correction System for Electron-Beam Projection Lithography by Cluster Processing

A fast proximity effect correction system for electron-beam projection lithography is developed. The following techniques are investigated to improve the performance; the patterns in each 250-µm-square subfield into which the original layout data is split, are corrected in parallel by a cluster system. Several subfields are processed at a time on one cluster node. Actual device data of a 70 nm system-on-a-chip is corrected by our proximity effect correction system to demonstrate its performance. The processing time for the proximity effect correction is reduced to 3.86 h from 60 h not only by using a cluster system with a 248 MHz processor ×8 nodes but also by processing 4×4 subfields simultaneously.

High-Speed Convolution System for Real-Time Proximity Effect Correction

In order to realize a real-time proximity effect correction system, a high-speed, highly accurate hardware system for convolution calculation has been developed. The representative figure method is used in the system. Pipeline architecture and parallel processing architecture are also used. The calculation speed of the system is 500 s for a writing region of 10 ×10 cm. The optimum correction dose has been evaluated using the output data of the convolution system. The error in the correction dose caused by our system is found to be 0.5% at most. These results suggest that a real-time proximity effect correction system can be realized, which can be used for making reticles of Gbit-class dynamic ramdom access memories (DRAMs).

Proximity effect correction data processing system for electron beam lithography

A proximity effect correction system has been developed by utilizing an efficient dose modulation technique based on a double Gaussian proximity function. A shaped electron beam system is assumed to be used. Two improvements are made. First, an optimal exposure dose on each pattern is determined by a new fast iterative method. The optimal dose makes the development isocontour conform to the pattern specification fairly well. Second, a ‘‘simple cell unit algorithm’’ that one of identical cells is proximity‐corrected, and the result is used to the other remaining cells is introduced. This offers to both decrease the processing time and save the memory/disk space. The present system is applied to the data processing of scaled‐down version of an aluminum wiring layer pattern of 16 Mbit dynamic random access memory with its minimum dimension of 0.4 μm. The calculation is successfully completed within 1 h of CPU time on a 10 MIPS general‐purpose computer. The dimensional accuracy of 10% is confirmed experimentally for the pattern including minimum features of 0.4 μm in the combination of trilayer resist process.

Electron Beam Direct Writing Technologies for 0.3-µm ULSI Devices

Electron beam direct writing technologies for 0.3-µm devices are studied in this paper. In order to prevent charging effects, TQV, which is a varnish consisting of 7, 7, 8, 8-tetracyano quino dimethane complex salt, has been coated on the top layer of a trilayer resist system. The effectiveness of TQV coating is indicated by the experimental results obtained from test patterns. A proximity effect correction system with several strategies to reduce the correction time and output data volume has been developed. These technologies have been adopted for the fabrication of ULSI circuit patterns with the dimension of about 0.3 µm. The calculation time and the output data volume of a proximity effect correction are reduced considerably by using new methods. It is revealed that 0.3-µm ULSI patterns can be precisely fabricated by these new technologies.

Proximity effect correction for an electron beam direct writing system EX-7

A new proximity effect correction software system has been developed, which is characterized by the usage of an approximate correction dose formula. The arrayed shot method was developed and a hierarchical data format was used to compact the amount of EB data. An inversion method has also been developed and a hierarchical pattern layout structure was used to accelerate the correction calculation speed. The proximity effect correction system has been installed into a high voltage electron beam direct writing system EX-7 and has been applied to some LSI patterns. The calculation time for correction was about 0.7 h for a 4 MDRAM and about 1 h for a 20 k gate array by using a 14 MIPS computer. The amount of EB data was about 40 Mbytes for the DRAM and about 50 Mbytes for the gate array.

Computer Aided Proximity Effect Correction System in Photolithography

Reflected light from step coverage causes fatal pattern defects in photolithography. The resist pattern defects are caused by the extra exposure from the highly reflective stepped substrate, such as breaks in the pattern of the aluminum layer. The problem is significant when the patterns in the different layers are near each other. We named this problem the proximity effect. The specific design rules such as the space between the resist pattern and the steps on the substrate are evaluated by simulation and experiment. Based on the evaluated results, we propose a computer aided proximity effect correction system to verify the pattern layout and eliminate the proximity effect. The effectiveness of the system is confirmed experimentally.