Proposed Multiplication Algorithm Research Articles

A Fast Multiplication Approach Using a Tree-Based Structure

This paper presents a technique for integer number multiplication using a tree-based structure. In the proposed method, both the generation of the partial products and the addition of partial products are completed in the tree structure. The proposed multiplication approach has been designed in two steps: Firstly, the partial products are generated in a tree-based structure using the fewest numbers of gates. Secondly, diagonal partial products additions have been done by the partial products residing in the diagonal partial product nodes to get a faster multiplication result, where two partial product nodes Pi , and Pk,l are diagonal only if |i - k| = |j - l|where i and k are the multiplicand bits; and j and l are the multiplier bits. The comparative study shows that the proposed multiplication algorithm outperforms the existing techniques; e.g., the proposed 4 × 4 multiplication algorithm improves 50% on the worst case running time complexity over the best known existing ones.
 GUB JOURNAL OF SCIENCE AND ENGINEERING, Vol 6(1), Dec 2019 P 20-26

Area-Time Efficient Hardware Implementation of Modular Multiplication for Elliptic Curve Cryptography

In this paper, an area-time efficient hardware implementation of modular multiplication over five National Institute of Standard and Technology (NIST)-recommended prime fields is proposed for lightweight elliptic curve cryptography (ECC). A modified radix-2 interleaved algorithm is proposed to reduce the time complexity of conventional interleaved modular multiplication. The proposed multiplication algorithm is designed in hardware and separately implemented on Xilinx Virtex-7, Virtex-6, Virtex-5, and Virtex-4 field-programmable gate array (FPGA) platforms. On the Virtex-7 FPGA, the proposed design occupies only 1151, 1409, 1491, 2355, and 2496 look up tables (LUTs) and performs single modular multiplication in 0.93 μs, 1.18 μs, 1.45 μs, 2.80 μs, and 4.69 μs with maximum clock frequencies of 207.1 MHz, 190.7 MHz, 177.3 MHz, 137.6 MHz, and 111.2 MHz over five NIST prime fields of size 192, 224, 256, 384, and 521 bits, respectively. The hardware implementations on the Virtex-6, Virtex-5, and Virtex-4 FPGAs also show that the proposed design is highly efficient in terms of hardware resource utilization and area-delay product compared with other designs for modular multiplication.

Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis

Efficient implementation of finite field multipliers based on a reordered normal basis (RNB) is highly desirable in the current/emerging cryptosystems since it offers almost free realization of squaring operation. Therefore, in this paper, we propose novel bit-parallel and digit-serial finite field multipliers over $GF(2^{m})$ based on RNB. By efficient transformation of the core multiplication algorithm using a unique circular shifting feature, we have derived an efficient algorithm for low-complexity systolic mapping. Both bit-parallel and digit-serial structures of the multipliers are then obtained and optimized to enhance the area–time efficiency. We have also utilized the unique feature of the proposed multiplication algorithm to obtain the systolic multipliers by Karatsubalike decomposition. Detailed analysis and comparison show the superior performance of the proposed implementation. For example, the proposed regular and Karatsuba-based bit-parallel designs involve at least 48.4% less area-delay product (ADP) and 42.2% less power-delay product (PDP) than the best existing ones (37.7% and 55.3% less ADP and PDP on field-programmable gate array platform), respectively. The proposed multipliers, because of their lower area–time complexities, can be used for efficient realization of cryptographic applications.

SSTL Input/Output Standard Based Energy Efficient Multiplier Design Using Urdhva Tiryagbhyam on 28nm FPGA

We have taken different set of frequencies and done study of power by varying frequencies and with different SSTL Standard Used for Input/Outputs at fixed temperature i.e. 25 degree Celsius. SSTL family includes SSTL15, SSTL18_II, SSTL135, SSTL12, SSTL18_I. Power has been calculated on these standards and analysis has been done to find the standard with least power consumption and to make an energy efficient device. The proposed multiplication algorithm is coded in Verilog, synthesized and simulated using Xilinx ISE design suit 14.2.at the end we can conclude that there can be 34-50% power consumption reduced by using frequency scaling technique and using SSTL Standard used for Input/Output. The maximum power has been consumed by SSTL18_II and minimum power consumption is by SSTL12.

Efficient Big Integer Multiplication and Squaring Algorithms for Cryptographic Applications

Public-key cryptosystems are broadly employed to provide security for digital information. Improving the efficiency of public-key cryptosystem through speeding up calculation and using fewer resources are among the main goals of cryptography research. In this paper, we introduce new symbols extracted from binary representation of integers called Big-ones. We present a modified version of the classical multiplication and squaring algorithms based on the Big-ones to improve the efficiency of big integer multiplication and squaring in number theory based cryptosystems. Compared to the adopted classical and Karatsuba multiplication algorithms for squaring, the proposed squaring algorithm is 2 to 3.7 and 7.9 to 2.5 times faster for squaring 32-bit and 8-Kbit numbers, respectively. The proposed multiplication algorithm is also 2.3 to 3.9 and 7 to 2.4 times faster for multiplying 32-bit and 8-Kbit numbers, respectively. The number theory based cryptosystems, which are operating in the range of 1-Kbit to 4-Kbit integers, are directly benefited from the proposed method since multiplication and squaring are the main operations in most of these systems.

Karatsuba-ZOT Multiplication Algorithm and its Application in Cryptography

The number theory based cryptography algorithms are the most commonly used public-key cryptosystems. One of the fundamental arithmetic operations for such systems is the large integer multiplication. The efficiency of these cryptosystems is directly related to the efficiency of this large integer multiplication operation. Classical multiplication algorithm and Karatsuba multiplication algorithm, and their hybrid, are among the most popular multiplication algorithms used for this purpose. In this paper, we propose a hybrid of Karatsuba and a classical-based multiplication algorithm, enhanced by a new number representation system. The new number representation, known as "Big-Digits”, is used to carry out the sub-multiplication operation in the new multiplication algorithm. Big-Digits has a compact representation with lower Hamming weight. As the result, the number of sub-multiplication operations for the multiplication algorithm that is based on the Big-Digits representation is significantly reduced. Our results show that the proposed multiplication algorithm is significantly faster than the classical, Karasuba and the hybrid of Karatsuba-Classical multiplication algorithms within the implementation domain of the public-key cryptography.

TinyECCK16: An Efficient Field Multiplication Algorithm on 16-bit Environment and Its Application to Tmote Sky Sensor Motes

Recently, the result of TinyECCK (Tiny Elliptic Curve Cryptosystem with Koblitz curve) shows that both field multiplication and reduction over GF(2m) are related to a heavy amount of duplicated memory accesses and that reducing the number of these duplications noticeably improves the performance of elliptic curve operations such as scalar multiplications, signing and verification. However, in case that the underlying word size is extended from 8-bit to 16-bit or 32-bit, the efficiency of the techniques proposed in TinyECCK is decreased because the number of memory accesses to load or store an element in GF(2m) is significantly reduced. Therefore, in this paper, we propose a technique which makes left-to-right (ltr) comb method which is widely used as an efficient multiplication algorithm over GF(2m) suitable for extended word sizes and present TinyECCK16 (Tiny Elliptic Curve Cryptosystem with Koblitz curve on 16-bit word) which is implemented with the proposed multiplication algorithm on 16-bit Tmote Sky mote. The proposed algorithm is faster than typical ltr comb method by 15.06% and the 16-bit version of the algorithm proposed in TinyECCK by 5.12% over GF(2163).

Low-complexity bit-parallel dual basis multipliers using the modified Booth’s algorithm

New bit-parallel dual basis multipliers using the modified Booth’s algorithm are presented. Due to the advantage of the modified Booth’s algorithm, two bits are processed in parallel for reduction of both space and time complexities. A multiplexer-based structure has been proposed for realization of the proposed multiplication algorithm. We have shown that our multiplier saves about 9% space complexity as compared to other existing multipliers if the generating polynomial is trinomial or all one polynomial. Furthermore, the proposed multiplier is faster than existing multipliers.

Efficient multiplication beyond optimal normal bases

In cryptographic applications, the use of normal bases to represent elements of the finite field GF(2/sup m/) is quite advantageous, especially for hardware implementation. In this article, we consider an important field operation, namely, multiplication which is used in many cryptographic functions. We present a class of algorithms for normal basis multiplication in GF(2/sup m/). Our proposed multiplication algorithm for composite finite fields requires a significantly lower number of bit level operations and, hence, can reduce the space complexity of cryptographic systems.

Novel Radix Finite Field Multiplier for GF(2 ^m )

In this paper, a new {\it High-Radix} Finite Field multiplication algorithm for GF(2^m) is proposed for the first time. The proposed multiplication algorithm can operate in a Digit-serial fashion, and hence can give a trade-off between the {\it speed}, the{\it area} , the input/output pin limitation, and the low power consumption by simply {\it varying} the digit size. A detailed example of a new Radix-16 GF(2^m) Digit-Serial multiplication architecture adopting the proposed algorithm illustrates a speed improvement of 75% when compared to conventional Radix-2 bit-serial realization. This is made more significant when it is noted that the speed improvement of 75% was achieved at the expense of only 2.3 times increase in the hardware requirements of the proposed architecture.