Proposed All-pass Filter Research Articles

Tunable Active Inductor-Based Second-Order All-Pass Filter as a Time Delay Cell for Multi-GHz Operation

In this paper, a CMOS wideband second-order voltage-mode all-pass filter as a time delay cell is proposed. The proposed all-pass filter is made up of solely two transistors as active elements and four passive components. This filter demonstrates a group delay of approximately 60 ps within a bandwidth of 5 GHz, achieving maximum delay–bandwidth product. The proposed circuit is highly linear and has an input-referred 1-dB compression point $$P_{1\mathrm{{dB}}}$$ of 2 dBm. The power consumption of the proposed circuit is only 10.3 mW. On the other hand, an active inductor is employed in the all-pass filter instead of a passive RLC tank; therefore, the three passive components are eliminated, in order to tune the time delay and improve the size. In this case, even though the power consumption increases, the time delay can be controlled across an improved bandwidth of approximately 10 GHz. Moreover, the circuit demonstrates a 1-dB compression point $$P_{1\mathrm{{dB}}}$$ of 18 dBm. The proposed all-pass filter is simulated in TSMC 180-nm CMOS process parameters.

5GHz CMOS All-Pass Filter-Based True Time Delay Cell

Analog CMOS time-delay cells realized by passive components, e.g., lumped LC delay lines, are inefficient in terms of area for multi-GHz frequencies. All-pass filters considered as active circuits can, therefore, be the best candidates to approximate time delays. This paper proposes a broadband first-order voltage-mode all-pass filter as a true-time-delay cell. The proposed true-time-delay cell is capable of tuning delay, demonstrating its potential capability to be used in different systems, e.g., RF beam-formers. The proposed filter achieves a flat group delay of over 60 ps with a pole/zero pair located at 5 GHz. This proposed circuit consumes only 10 mW power from a 1.8-V supply. To demonstrate the performance of the proposed all-pass filter, simulation results are conducted by using Virtuoso Cadence in a standard TSMC 180-nm CMOS process.

Single DV-DXCCII Based Voltage Controlled First Order All-pass Filter with Inverting and Non-inverting responses

In this paper, a new voltage controlled first order all-pass filter is presented. The proposed circuit employs a single Differential Voltage Dual-X second generation Current Conveyor (DV-DXCCII), a NMOS (n-type Metal Oxide Semiconductor) transistor operated in the triode region as an active resistor and a grounded capacitor. The proposed all-pass filter provides both inverting and non inverting voltage-mode outputs simultaneously from the same configuration without any matching constraint. Non-ideal analysis along with sensitivity analysis is investigated. The proposed circuit has low active and passive sensitivities. The Monte Carlo analysis is also done for showing good sensitivity performances of the proposed circuit. In addition, to utilize the feature of cascadability, an application of higher order filter is also given. Moreover, the use of grounded capacitor makes the proposed circuit particularly attractive for Integrated Circuit (IC) implementation point of view. The theoretical results are validated through PSPICE simulations with TSMC 0.18 μm Complementary Metal Oxide Semiconductor (CMOS) process parameters.

High Performance Voltage-Mode Tunable All-Pass Section

This paper presents a voltage-mode (VM) tunable all-pass section, employing a grounded capacitor and a newly introduced current conveyor with an extra X stage. The proposed all-pass filter uses grounded capacitor as the only passive component and benefits from high input and low output impedance. The proposed circuit exhibits eight performance features without trade-offs, as compared to carefully chosen 25 published works. The functionality of the proposed element is verified through PSPICE simulation using 0.25-μm process parameters. An application of second order is also incorporated.

All-pass filters realised using the current-controlled CCII with intrinsic negative resistance

Novel first-order all-pass filter configurations are introduced in this article for the first time using CCIIs with negative intrinsic resistance. The first one offers the benefit of the high-impedance input with a simultaneous reduction of the number of required passive elements. In addition, one current conveyor and an appropriate adder are required instead of the two current conveyors employed in the corresponding earlier topology. The second proposed all-pass filter has the attractive characteristic, in comparison with those already published in the literature, that only a single current conveyor is required. In both these configurations, a single grounded resistor is required as a passive element. Thus, these configurations can be made resistorless using metal-oxide semiconductor field-effect transistors and, also the condition of realisability can be electronically satisfied.

First-order allpass filter and sinusoidal oscillators using DDCCs

A voltage-mode first-order allpass filter using one differential difference current conveyor (DDCC), one grounded capacitor and one floating resistor is presented. No passive component matching constraints are required. Because the output impedance of the proposed allpass filter is low, the output terminal can be directly connected to the next stage. Using the proposed first-order allpass filter as a basic building block, a new quadrature oscillator and even-phase sinusoidal oscillators can be obtained. The simulation results confirm the theoretical analysis.

Closed-Form Design of All-Pass Fractional Delay Filters

In this letter, we propose a novel all-pass (AP) fractional delay filter whose denominator polynomial is obtained by truncating the power series of a certain function. This function is derived from the frequency response of the denominator whose magnitude response is related to the desired phase response through the Hilbert transform since the denominator of a stable AP filter is of minimum phase. The target function and corresponding power series are calculated analytically and expressed in closed form. The closed-form expressions facilitate the analysis of stability. According to the properties for the coefficients of the denominator polynomial, we show that the proposed AP filter is stable for positive delay. Numerical examples indicate that the phase delays of the proposed filters are flat around DC.