Propagation Delay Of Interconnects Research Articles

Ultralow-${k}$ Dielectric With Structured Pores for Interconnect Delay Reduction

An ultralow- ${k}$ dielectric using structured pores to reduce interconnect propagation delay is demonstrated. By using a carbon nanotube (CNT) template, porous oxide with vertical cylindrical pores is formed on the Si3N4 etch-stop layer and successfully integrated with the copper damascene process. The resulting dielectric is anisotropic with an interlayer dielectric constant of k = 1.97 and an intralayer dielectric constant of k = 1.75 at a porosity of 65%. Compared with the conventional porous material with randomly arranged spherical pores, a much higher elastic modulus of 15.7 GPa is achieved to allow the chemical mechanical polish process at a porosity of 65%.

Fibonacci Codes for Crosstalk Avoidance

In the deep sub micrometer CMOS process technology, the interconnect resistance, length, and inter- wire capacitance are increasing significantly, which contribute to large on-chip interconnect propagation delay. Data transmitted over interconnect determine the propagation delay and the delay is very significant when adjacent wires are transitioning in opposite directions (i.e., crosstalk transitions) as compared to transitioning in the same direction. Propagation delay across long on-chip buses is significant when adjacent wires are transitioning in opposite direction (i.e., crosstalk transitions) as compared to transitioning in the same direction. By exploiting Fibonacci number system, we propose a family of Fibonacci coding techniques for crosstalk avoidance, relate them to some of the existing crosstalk avoidance techniques, and show how the encoding logic of one technique can be modified to generate code words of the other technique. Keywords: On-chip bus, crosstalk, Fibonacci coding.

Redundant Vias Insertion for Performance Enhancement in 3D ICs

Three dimensional (3D) integrated circuits (ICs) have the potential to significantly enhance VLSI chip performance, functionality and device packing density. Interconnects delay and signal integrity issues are critical in chip design. In this paper, we extend the idea of redundant via insertion of conventional 2D ICs and propose an approach for vias insertion/placement in 3D ICs to minimize the propagation delay of interconnects with the consideration of signal integrity. The simulation results based on a 65nm CMOS technology demonstrate that our approach in general can result in a 9% improvement in average delay and a 26% decrease in reflection coefficient. It is also shown that the proposed approach can be more effective for interconnects delay improvement when it is integrated with the buffer insertion in 3D ICs.

Study of swing potential on deep submicron on-chip interconnect

The low energy limit of signal on deep submicron on-chip interconnect is deduced from Shannon's communication theorem considering the influence of noise. Based on this energy limit, the analytic model of minimum swing potential considering transmission line effects is constructed. Applying the analytic model to interconnect in deep submicron technology nodes from 0.18 to 0.05 μm, it is shown that the swing potential with present low-swing technique such as SDVST could be reduced further by 70–95% according to the analysis of this work. Correspondingly, by using the low-swing interconnect technique with the minimum swing potential obtained in this work, the decrement of interconnect dynamic power dissipation can be further decreased by about 10–20% of their original one by using SDVST technique, and that of interconnect propagation delay, by one third. Furthermore, the maximum interconnect length is evaluated with a minimum swing potential value in interconnect design. All the results are valuable for interconnect performance optimization, such as repeater insertion in deep submicron circuits. As an application, the design of low swing potential interconnect with interface circuit is introduced.