Promising Candidate For Future Memory Research Articles

CMOS Compatible Bio-Realistic Implementation with Ag/HfO2-Based Synaptic Nanoelectronics for Artificial Neuromorphic System

The emerging resistive switching devices have attracted broad interest as promising candidates for future memory and computing applications. Particularly, it is believed that memristor-based neuromorphic engineering promises to enable efficient artificial neuromorphic systems. In this work, the synaptic abilities are demonstrated in HfO2-based resistive memories for their multi-level storage capability as well as being compatible with advanced CMOS technology. Both inert metal (TaN) and active metal (Ag) are selected as top electrodes (TE) to mimic the abilities of a biological synapse. HfO2-based resistive memories with active TE exhibit great advantages in bio-realistic implementation such as suitable switching speed, low power and multilevel switching. Moreover, key features of a biological synapse such as short-term/long-term memory, “learning and forgetting”, long-term potentiation/depression, and the spike-timing-dependent plasticity (STDP) rule are implemented in a single Ag/HfO2/Pt synaptic device without the poorly scalable software and tedious process in transistors-based artificial neuromorphic systems.

Memristive computing devices and applications

Advances in electronics have revolutionized the way people work, play and communicate with each other. Historically, these advances were mainly driven by CMOS transistor scaling following Moore’s law, where new generations of devices are smaller, faster, and cheaper, leading to more powerful circuits and systems. However, conventional scaling is now facing major technical challenges and fundamental limits. New materials, devices, and architectures are being aggressively pursued to meet present and future computing needs, where tight integration of memory and logic, and parallel processing are highly desired. To this end, one class of emerging devices, termed memristors or memristive devices, have attracted broad interest as a promising candidate for future memory and computing applications. Besides tremendous appeal in data storage applications, memristors offer the potential to enable efficient hardware realization of neuromorphic and analog computing architectures that differ radically from conventional von Neumann computing architectures. In this review, we analyze representative memristor devices and their applications including mixed signal analog-digital neuromorphic computing architectures, and highlight the potential and challenges of applying such devices and architectures in different computing applications.

Resistance random access memory

Non-volatile memory (NVM) will play a decisive role in the development of the next-generation of electronic products. Therefore, the development of next-generation NVM is urgent as widely applied flash memory is facing its physical limit. Among various next-generation NVMs, Resistive Random Access Memory (RRAM) is a promising candidate for future memory due to its high-efficiency, high-speed and energy-saving characteristics. In recent years, continuous improvement and in-depth investigation in both materials and electrical switching mechanisms have not only lead to a breakthrough in the performance of digital NVM, but also lead to other possible memory functionality. This paper describes new findings and perspectives on various RRAM devices with different laminated structures and materials, and classifies RRAM into four categories according to different resistive switching mechanisms, from which the four elements are (1) anion-type RRAM: redox reaction and migration of oxygen ions, (2) cation-type RRAM: redox reaction and migration of cation ions, (3) carbon-based RRAM: the stretch of C C bond lengths due to oxygen and hydrogen dual ions, (4) oxide-based electrode: oxygen accumulation in oxide-based electrode.

Biorealistic Implementation of Synaptic Functions with Oxide Memristors through Internal Ionic Dynamics

Memristors have attracted broad interest as a promising candidate for future memory and computing applications. Particularly, it is believed that memristors can effectively implement synaptic functions and enable efficient neuromorphic systems. Most previous studies, however, focus on implementing specific synaptic learning rules by carefully engineering external programming parameters instead of focusing on emulating the internal cause that leads to the apparent learning rules. Here, it is shown that by taking advantage of the different time scales of internal oxygen vacancy (VO) dynamics in an oxide‐based memristor, diverse synaptic functions at different time scales can be implemented naturally. Mathematically, the device can be effectively modeled as a second‐order memristor with a simple set of equations including multiple state variables. Not only is this approach more biorealistic and easier to implement, by focusing on the fundamental driving mechanisms it allows the development of complete theoretical and experimental frameworks for biologically inspired computing systems.

Retention failure analysis of metal-oxide based resistive memory

Resistive switching devices (RRAMs) have been proposed a promising candidate for future memory and neuromorphic applications. Central to the successful application of these emerging devices is the understanding of the resistance switching and failure mechanism, and identification of key physical parameters that will enable continued device optimization. In this study, we report detailed retention analysis of a TaOx based RRAM at high temperatures and the development of a microscopic oxygen diffusion model that fully explains the experimental results and can be used to guide future device developments. The device conductance in low resistance state (LRS) was constantly monitored at several elevated temperatures (above 300 °C), and an initial gradual conductivity drift followed by a sudden conductance drop were observed during retention failure. These observations were explained by a microscopic model based on oxygen vacancy diffusion, which quantitatively explains both the initial gradual conductance drift and the sudden conductance drop. Additionally, a non-monotonic conductance change, with an initial conductance increase followed by the gradual conductance decay over time, was observed experimentally and explained within the same model framework. Specifically, our analysis shows that important microscopic physical parameters such as the activation energy for oxygen vacancy migration can be directly calculated from the failure time versus temperature relationship. Results from the analytical model were further supported by detailed numerical multi-physics simulation, which confirms the filamentary nature of the conduction path in LRS and the importance of oxygen vacancy diffusion in device reliability. Finally, these high-temperature stability measurements also reveal the existence of multiple filaments in the same device.

Throughput Enhancement for Phase Change Memories

Phase Change Memory (PCM) has emerged as a promising candidate for future memories. PCM has high cell density, zero cell leakage, and high stability in deep sub-micron technologies. Although PCM has limited endurance, recent endeavors have shown that its lifetime can be improved by orders of magnitude. However, a major hurdle for PCM is the long write latency and high write power. For this reason, PCM cannot deliver satisfactory memory bandwidth for high-end computing environment such as multi-processing and server systems. In this paper, we develop a non-blocking PCM bank design such that subsequent reads or writes can be carried in parallel with an on-going write. This is effective in removing long blocking time due to serial operations. Moreover, we propose novel memory request scheduling algorithms to exploit intra-bank parallelism brought by our non-blocking hardware. Our non-blocking hardware with scheduling enhancement improves PCM memory throughput by 51% on average. Finally, we propose a fine-grained power budgeting scheme to achieve more throughput improvement under power budgets. Experiments show that our scheduler enhanced with power budgeting scheme can achieve a throughput improvement of 118% on average.

Random telegraph noise and resistance switching analysis of oxide based resistive memory

Resistive random access memory (RRAM) devices (e.g."memristors") are widely believed to be a promising candidate for future memory and logic applications. Although excellent performance has been reported, the nature of resistance switching is still under extensive debate. In this study, we perform systematic investigation of the resistance switching mechanism in a TaOx based RRAM through detailed noise analysis, and show that the resistance switching from high-resistance to low-resistance is accompanied by a semiconductor-to-metal transition mediated by the accumulation of oxygen-vacancies in the conduction path. Specifically, pronounced random-telegraph noise (RTN) with values up to 25% was observed in the device high-resistance state (HRS) but not in the low-resistance state (LRS). Through time-domain and temperature dependent analysis, we show that the RTN effect shares the same origin as the resistive switching effects, and both can be traced to the (re)distribution of oxygen vacancies (VOs). From noise and transport analysis we further obtained the density of states and average distance of the VOs at different resistance states, and developed a unified model to explain the conduction in both the HRS and the LRS and account for the resistance switching effects in these devices. Significantly, it was found that even though the conduction channel area is larger in the HRS, during resistive switching a localized region gains significantly higher VO and dominates the conduction process. These findings reveal the complex dynamics involved during resistive switching and will help guide continued optimization in the design and operation of this important emerging device class.

Oxide Heterostructure Resistive Memory

Resistive switching devices are widely believed as a promising candidate for future memory and logic applications. Here we show that by using multilayer oxide heterostructures the switching characteristics can be systematically controlled, ranging from unipolar switching to complementary switching and bipolar switching with linear and nonlinear on-states and high endurance. Each layer can be tailed for a specific function during resistance switching, thus greatly improving the degree of control and flexibility for optimized device performance.