Progress In Semiconductor Technology Research Articles

Analyses of BER-referred noise-to-signal ratio in online measurements of high-baud-rate coherent receivers.

Digital coherent transmission features a very large transmission bandwidth and has played a main role in core optical transmission networks. With the progress of semiconductor technologies, practical coherent transceivers with rates over 100 Gbaud are becoming feasible. With such advances, the transceiver components must have lower power consumption and lower costs, and it becomes important to know how each component contributes to the overall transmission performance. Here, to decompose the effects of noise factors in high-baud-rate DP-16QAM transmissions, we used the theoretical relationship between the bit error rate (BER) and noise-to-signal ratio (NSR) and performed linear analyses. The NSR could be decomposed into individual noise contributions according to dependences on the inverse signal and local photocurrents. The obtained parameters were shown to be useful for predicting required optical signal-to-noise ratio (ROSNR) characteristics.

Leakage Current Reduction in CMOS Circuits Using Stacking Technique

This paper deals with The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology. There by the extremely complex functionality is enabled to be integrated on a single chip. So, transistor size is reduced to few nanometers. By reducing the size drastically some problems are occurred. In that leakage power is one of the disadvantage. By using this stacking technique we are going to reduce the leakage currents.

Embedded systems codesign under artificial intelligence perspective: a review

Intelligent embedded systems (IES) and their distributed versions, represent a novel and promising generation of embedded systems. IES have the capacity of reasoning about their external environments and adapt their behaviour accordingly. Such systems are situated in the intersection of two different branches, which are the embedded computing and the intelligent computing. On the other hand, intelligent embedded software (IESo) is becoming a large part of the engineering cost of intelligent embedded systems. IESo can include some artificial intelligence-based systems such as expert systems, neural networks and other sophisticated artificial intelligence (AI) models to guarantee some important characteristics such as self-learning, self-optimising and self-adaptation. Despite, the wide spread of such systems, some design challenging issues are arising. Designing a resource constrained software and at the same time intelligent is not a trivial task especially in a real-time context. To deal with this dilemma, embedded systems researchers have profited from the progress in semiconductor technology to develop specific hardware to support well AI models and render the integration of AI with the embedded world a reality.

Embedded systems codesign under artificial intelligence perspective: a review

Intelligent embedded systems (IES) and their distributed versions, represent a novel and promising generation of embedded systems. IES have the capacity of reasoning about their external environments and adapt their behaviour accordingly. Such systems are situated in the intersection of two different branches, which are the embedded computing and the intelligent computing. On the other hand, intelligent embedded software (IESo) is becoming a large part of the engineering cost of intelligent embedded systems. IESo can include some artificial intelligence-based systems such as expert systems, neural networks and other sophisticated artificial intelligence (AI) models to guarantee some important characteristics such as self-learning, self-optimising and self-adaptation. Despite, the wide spread of such systems, some design challenging issues are arising. Designing a resource constrained software and at the same time intelligent is not a trivial task especially in a real-time context. To deal with this dilemma, embedded systems researchers have profited from the progress in semiconductor technology to develop specific hardware to support well AI models and render the integration of AI with the embedded world a reality.

Flywheel Energy Storage System Using Magnetic Levitation

This paper deals with the voltage sag compensator in a system using flywheel energy storage system technology by using partial magnetic levitation. Voltage fluctuates in a generator from second to second and due to these fluctuations, it becomes difficult to meet the consumer demand since they account to high current losses. In such a case, Flywheels are used where energy is stored mechanically and transferred to and from the flywheel by an integrated motor/generator. Today flywheels are used as supplementary UPS storage at several industries world over. Future applications span a wide range including electric vehicles, intermediate storage for renewable energy generation and direct grid applications from power quality issues to offering an alternative to strengthening transmission. One of the key advantages of flywheel is that it compensates for the losses of the system by its storage mechanism and thus high overall efficiency is attained. When voltage is increased, current losses are reduced and transformer steps become redundant. Recent progress in semi-conductor technology enables faster switching and lower costs. Flywheel with magnetic bearings using magnetic levitation has been introduced for effectiveness of the system and to overcome frictional losses. The predominant parts of prior studies have been directed towards optimizing mechanical issues whereas the electro technical part now seems to show great potential for improvement. An overview of flywheel technology and previous projects are presented and moreover a 200kW flywheel using high voltage technology is simulated.

Comparison of Leakage Power Reduction Techniques in 65nm Technologies

The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over the world today, the battery-powered electronic system forms the backbone. To maximize the battery life, the tremendous computational capacity of portable devices such as notebook computers, personal communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has to be realized with very low power requirements. Leakage power consumption is one of the major technical problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power minimization techniques have been presented in this paper comparison of Leakage reduction technique is developed in Cadence Virtuoso in 65nm regime with the combination of stack with sleepy keeper approach with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%, Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24% with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.

Leakage Power Reduction Using Sleepy StackPower Gating Technique

The project presents the power gating techniques used for leakage power reduction.The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over the world today, the battery-powered electronic system forms the backbone. To maximize the battery life, the tremendous computational capacity of portable devices such as notebook computers, personal communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has to be realized with very low power requirements. Leakage power consumption is one of the major technical problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power minimization techniques have been presented in this paper a novel Leakage reduction technique is developed in Tanner EDA tool.

Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip

The continued push to smaller geometries, higher frequencies, and larger chip sizes rapidly resulted in an incompatibility between interconnect needs and projected interconnect performance. As stated in the 2003 International Technology Roadmap for Semiconductors (ITRS'03) report, revolutionary interconnect methodologies such as radio frequency (RF)/wireless will deliver the foreseen progress in semiconductor technology. Recent advances in silicon integrated circuit technique are making possible tiny low-cost transceivers to be integrated on chip, namely radio-on-chip (ROC) technology. This paper proposes the idea of using wireless radios to transmit test data and control signals to resolve the acerbated core accessibility problem. Three types of wireless test micronetworks are first presented, i.e., miniature wireless local area network (LAN), multihop wireless test control network (MTCNet), and distributed multihop MTCNet. Then, the test control overhead and system resource partitioning in on-chip wireless micronetworks are analyzed. Several challenging system design problems such as RF node placement, core clustering, and control routing are studied, and the test control resources (i.e., the on-chip RF nodes for intrachip communication) are properly distributed and system optimization is performed in terms of test control cost. A simulation study shows the feasibility and applicability of intrachip MTCNet

Integrating power devices into silicon roadmaps

Although silicon roadmaps have had a major impact on the progress of semiconductor technology, roadmap emphasis has largely been in the digital arena. Integration of high-voltage and high-current devices into chip designs has tended to follow the original roadmap with a delay of a year or more owing to both economic and technological factors. The resulting 'mixed-signal' roadmaps tend to be less structured company-to-company, since more opportunities exist for a variety of approaches. To aid in the understanding of mixed-signal roadmaps, this paper summarises some of the requirements for including power devices into an existing BiCMOS technology. Some of the principles that determine the integration process are described.

Microcomputer Based Control of Frequency Regulator in Induction Motors

The progress of semiconductor technology and control systems the last years has made possible the realisation of highly efficient and low priced microprocessor-based controllers for the control of asynchronous motors. This paper describes the design and realization of a microcomputer-based device for frequency regulation of an asynchronous motor. Through the regulation of motor's supply frequency is achieved regulation of its speed. The control is based on PWM method, with voltage feedback, and frequency regulation is performed in the range of 20Hz to 60 Hz. The application platform is an automatic industrial press machine in a machines constructions company.

Communication ICs — market leaders in microelectronics

In recent years communication ICs became the fastest growing semiconductor market segment mainly driven by personal wireless communication products like pagers or mobile phones and internet applications with their permanent demand on increasing bandwidth. The high volume consumer market and its demand for low-cost, low-power, and highly integrated solutions had stimulated RF design engineers all over the world to develop novel integrated solutions for communication devices with an innovative advance that is more close to Moore’s law than it was in the past. This was made possible once by a great progress in semiconductor technology, where well established silicon and silicon bipolar technologies extend the operating range steadily up to higher frequencies in the GHz range at the expense of GaAs technology which is driven back to niche products like power amplifiers and to communication techniques in the 40-Gbits/s range and above. On the other hand the integration of a complete system with a single technology has also consequences to the topology of the system and that has led to fundamental changes in system design procedures, which are treated by more sophisticated design tools which cover both system and circuit design and bring them close together. In this paper some actual trends in the development of communication ICs are presented and examples of recently published devices are given.

Tagged communication and synchronization memory for multiprocessor‐on‐a‐chip

AbstractMultiprocessor‐on‐a‐chip is becoming possible due to progress in semiconductor technologies. In the multiprocessor, the threaded parallel processing requires decreasing the overhead of interthread communication and synchronization. We propose the tagged communication and synchronization memory with the access counter using CAM (TCSM) which supports a high‐speed mechanism for the mutual exclusion, the condition synchronization, the barrier synchronization, and the multicasting between the threads. TCSM allocates its entries dynamically and ensures the producer–consumer synchronization by valid/invalid state in the access count. The execution environment of the threads is protected because the tag of TCSM is used for identifying both the task which threads belong to and the storage used by threads. The MTA/TCSM multichip multiprocessor system has been developed to evaluate the multiprocessor‐on‐a‐chip including TCSM. As a result of the evaluation on MTA/TCSM, the overhead of interthread synchronization and communication using TCSM is lower than using the conventional shared memory. © 2001 Scripta Technica, Syst Comp Jpn, 32(4): 1–13, 2001

On-Line Fault Detection of Inverter-Fed Induction Motors Using Advanced Signal Processing Techniques

Due to the increasing demands concerning reliability, safety and economy of technical processes, on-line fault detection of induction motors is an important topic in the engineering field. Approaches, based on the spectral analysis of motor currents have been frequently proposed. The main drawback of these approaches has been the restriction on induction machines fed by power supplies with constant frequency. Due to the progress in semiconductor technology and power electronics, inverter-fed induction motors providing a wide speed range are more and more employed. This paper proposes the basics of a nonlinear time-domain transformation which is capable of applying the same spectral analysis scheme for different speeds. Finally, experiments are shown for the detection of insulation failures in the stator windings.

A multi-campus virtual corporate laboratory

The US Semiconductor Industries Association, Semiconductor Equipment Manufacturing Institute and Department of Defense have jointly established a pioneering new long range research effort identified as the Focus Center Research Program (FCRP). In late 1998 the Interconnect Focus Center (IFC) was established at MIT, Stanford University, Rensselaer Polytechnic Institute, State University of New York at Albany, Cornell University and Georgia Institute of Technology (GIT) with GIT serving as the prime contracting university. The overarching goal of the IFC is to discover and invent new solutions that will enable the US semiconductor industry to transcend known limits on interconnections (between billions of transistors in a single silicon microchip) that would otherwise decelerate or halt the historical rate of progress of semiconductor technology.

Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic

Quantum-effect devices utilizing resonant tunneling are promising candidates for future nano-scale integration. Originating from the technological progress of semiconductor technology, circuit architectures with reduced complexity are investigated by exploiting the negative-differential resistance of resonant tunneling devices. In this paper a resonant tunneling device threshold logic family based on the Monostable-Bistable Transition Logic Element (MOBILE) is proposed and applied to different parallel adder designs, such as ripple carry and binary carry lookahead adders. The basic device is a resonant tunneling transistor (RTT) composed of a resonant tunneling diode monolithically integrated on the drain contact layer of a heterostructure field effect transistor. On the circuit level the key components are a programmable NAND/NOR logic gate, threshold logic gates, and parallel counters. The special properties of MOBILE logic gates are considered by a bit-level pipelined circuit style. Experimental results are presented for the NAND/NOR logic gate.

Effect of lead acetate concentration on the droplet size in liquid source misted chemical deposition

The needs for high quality, multi-component thin film are ever increasing with the progress of semiconductor technology. Liquid source misted chemical deposition (LSMCD) is a promising method for thin film preparation. However, the details of the characteristics of the droplets before depositing on the substrate have not been clearly understood. In this study, the effect of the solute on the droplet size was investigated with lead acetate, which is common starting material for the preparation of thin films of PbTiO 3, Pb(Zr, Ti)O 3, (Pb, La)(Zr, Ti)O 3 by sol–gel method. All of the produced droplets had size less than 10 μm. The mean diameter decreased with solution concentration, which is caused by the changes of the physical properties such as surface tension and density. Power law relationship was held between mean diameter and the ratio of surface tension and density. The exponent was 0.33 and 0.66 for 2-methoxyethanol and methanol, respectively.

電算機・通信利用技術の進歩

In the past ten years, the rapid progress in semiconductor technology has enabled the explosive growth in the performance and capability of computers. During this period, corporate information have evolved from host-centered to client-server due to the movement toward open systems and downsizing of computer systems. Recently, the technology innovation in repeated every day in the field of Internet technology. As a result, Internet technologies have been applied to all kinds of information and communication systems. Today, the information system environment is confronted with a wave of unprecedented change. This paper gives an overview of the recent progress in computer and communication technology, and describes how Daido Steel has applied these new technologies.

Built-in self-test: Early developments and future trends

This paper describes the early developments of Built-In Self-Test in retrospect and gives an outlook on future trends of this technique. The steps for eliminating the initial shortcomings, like silicon overhead, aliasing, and inefficient test patterns, which hindered the quick acceptance of self-test are discussed. New test challenges which are likely to be induced by the rapid progress in semiconductor technology are described. It is outlined how these problems can be solved by self-test.

Digital imaging for scanning electron microscopy

AbstractThe development and application of digital imaging technology has been one of the major advancements in scanning electron microscopy (SEM) during the past several years. This digital revolution has been brought about by significant progress in semiconductor technology, notably the availability of less expensive, high‐density memory chips and the development of inexpensive, high‐speed, analog‐to‐digital and digital‐to‐analog converters, mass storage, and high‐performance central processing units. This paper reviews a number of the advantages presented by digital imaging as applied to the SEM and describes a system developed at the National Institute of Standards and Technology for this purpose.

Associative controlling of monolithic parallel processor architectures

The VLSI implementation of monolithic parallel processor architectures is supported by the ongoing progress of semiconductor technology. Nevertheless, a cost efficient realization of flexible parallel processors, suitable for a broad range of video processing applications, requires efficient schemes for controlling of the provided parallel data paths. Therefore, a novel associative controlling scheme is presented. This approach enables an efficient implementation of monolithic parallel processors at reasonable hardware cost. The paper presents performance data of associative controlling based on a simplified model in comparison to alternative controlling schemes, like SIMD, MIMD, SPMD, and MSIMD. Furthermore, an overview of the architecture of the currently developed associatively controlled PRISMA video signal processor is given. >