Programmable Synaptic Weights Research Articles

An Event-Based Neural Network Architecture with Content Addressable Memory

A hybrid analog/digital very large-scale integration (VLSI) implementation of a spiking neural network with programmable synaptic weights was designed. The synaptic weight values are stored in an asynchronous module, which is interfaced to a fast current-mode event-driven DAC for producing synaptic currents with the appropriate amplitude values. It acts as a transceiver, receiving asynchronous events for input, performing neural computations with hybrid analog/digital circuits on the input spikes, and eventually producing digital asynchronous events in output. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the address event representation (AER). Using this representation, it is possible to interface the device to a workstation or a microcontroller and explore the effect of different types of spike-timing dependent plasticity (STDP) learning algorithms for updating the synaptic weights values in the CAM module.

Energy‐Efficient Organic Ferroelectric Tunnel Junction Memristors for Neuromorphic Computing

AbstractEnergy efficiency, parallel information processing, and unsupervised learning make the human brain a model computing system for unstructured data handling. Different types of oxide memristors can emulate synaptic functions in artificial neuromorphic circuits. However, their cycle‐to‐cycle variability or strict epitaxy requirements remain a challenge for applications in large‐scale neural networks. Here, solution‐processable ferroelectric tunnel junctions (FTJs) with P(VDF‐TrFE) copolymer barriers are reported showing analog memristive behavior with a broad range of accessible conductance states and low energy dissipation of 100 fJ for the onset of depression and 1 pJ for the onset of potentiation by resetting small tunneling currents on nanosecond timescales. Key synaptic functions like programmable synaptic weight, long‐ and short‐term potentiation and depression, paired‐pulse facilitation and depression, and Hebbian and anti‐Hebbian learning through spike shape and timing‐dependent plasticity are demonstrated. In combination with good switching endurance and reproducibility, these results offer a promising outlook on the use of organic FTJ memristors as building blocks in artificial neural networks.

Guest Editorial

This special issue on advances in design of ultra-low power circuits and systems il- lustrates a broad spectrum of challenges facing designers of high-performance and energy-efficient circuits in emerging technologies. Seeking to improve both the energy efficiency and throughput density, designers have turned to optimization methods tar- geting devices with interconnects to system-level power savings. The articles in this issue represent the cross-layer approach and span various emerging technologies, novel devices, and architectures. This issue contains eight scholarly articles, the experimental results of which show potential/promise to be ultra energy-efficient through innovation in device, logic, and architecture without compromising performance. Each manuscript was assigned to at least three reviewers and has undergone two or more rounds of revisions in the peer- review process. Overall 26 manuscripts were submitted and the following eight articles were selected based on the reviews and scope/fit into the special issue. Gaillardon et al., present a transversal survey on energy-efficient techniques ranging from devices to architectures. They look into various novel device architectures such as fully depleted planar devices, trigate geometries and gate-all-around structures that can allow reaching a high level of performance while reducing power consumption. Exploiting such devices can also lead to innovative circuits and architectural-level power management solutions like adaptive voltage and frequency scaling. Sitik et al., present a 20nm FinFET-based low-swing clocking methodology to pre- serve the dynamic power savings of low-swing clocking while minimizing the effect of leakage power consumption, clock skew, and timing violations. The technique reveals the premise for low-power/high-performance applications while achieving substantial power savings at high switching frequencies. Zhang et al., explore resource pooling where multiple architectural components are shared among the cores for improving system energy efficiency and reducing total chip area for 3D multicore processors. They present a 3D multicore architecture with poolable cache resources and introduce a runtime management policy to improve en- ergy efficiency of 3D systems. Khasanvis et al., introduce a low-power multi-state memory concept based on graphene crossbar devices. They present a multi-state memory design that can store multiple bits in a single cell. This work exploits a bilayer graphene nano-ribbon cross- bar tunneling device that exhibits negative differential resistance and hence can be used as multi-valued logic, which can be implemented along with CMOS lithography. Kang et al., present an overview of the spin-based devices and circuits by adding the spin freedom of electrons for usages such as memories and logic for achieving ultra-low power systems. This tutorial addresses various spin-based memory and logic systems; toggle MRAM, various from of STT-MRAM, Domain-wall systems, Spin-wave logic, partial/dynamic reconfigurable logic systems, and a neuromorphic framework to name a few. Azghadi et al., present a novel neuromorphic system based on a programmable neu- romorphic VLSI device that is comprise of silicon neurons and event-driven synapses, with programmable synaptic weight circuits. The device and neuromorphic system present a real-time low-power computing platform for exploring embedded neuromor- phic event-driven computational systems. Graziano et al., investigate molecular quantum-dot cellular automata (mQCA) as an emerging paradigm for high-performance low-power nanoscale computations. They provide a thorough analysis of mQCA-based circuits and a first assessment on the energy of a mQCA which is the most promising feature of this technology. At the system level, Le et al., investigate energy harvesting techniques for designing autonomous wireless sensor networks. The authors have presented an efficient energy harvesting system, which is compatible with various environmental sources such as light, heat, or wind.

Application of Silicon-Germanium Source Tunnel-FET to Enable Ultralow Power Cellular Neural Network-Based Associative Memory

This paper studies the application of tunnel FET (TFET) in designing a low power and robust cellular neural network (CNN)-based associative memory (AM). The lower leakage, steeper switching slope, and higher output resistance of TFET are exploited in designing an ultralow-power TFET-based operational transconductance amplifier (OTA). A TFET-OTA is utilized as a programmable synaptic weight multiplier for CNN. The ultralow-power of TFET-OTA enables a higher connectivity network even at a lower power, and thereby improves the memory capacity and input pattern noise tolerance of CNN-AM for low power applications. The TFET-based higher connectivity CNN also exploits the unique characteristics of TFET to improve the throughput efficiency of CNN-AM.

An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory

We present a hybrid analog/digital very large scale integration (VLSI) implementation of a spiking neural network with programmable synaptic weights. The synaptic weight values are stored in an asynchronous Static Random Access Memory (SRAM) module, which is interfaced to a fast current-mode event-driven DAC for producing synaptic currents with the appropriate amplitude values. These currents are further integrated by current-mode integrator synapses to produce biophysically realistic temporal dynamics. The synapse output currents are then integrated by compact and efficient integrate and fire silicon neuron circuits with spike-frequency adaptation and adjustable refractory period and spike-reset voltage settings. The fabricated chip comprises a total of 32 × 32 SRAM cells, 4 × 32 synapse circuits and 32 × 1 silicon neurons. It acts as a transceiver, receiving asynchronous events in input, performing neural computation with hybrid analog/digital circuits on the input spikes, and eventually producing digital asynchronous events in output. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the Address Event Representation (AER). Using this representation it is possible to interface the device to a workstation or a micro-controller and explore the effect of different types of Spike-Timing Dependent Plasticity (STDP) learning algorithms for updating the synaptic weights values in the SRAM module. We present experimental results demonstrating the correct operation of all the circuits present on the chip.

Sensitivity study and improvements on a nonlinear resistive-type neuron circuit

A generalised VLSI circuit realisation for a nonlinear active resistor-type neuron is proposed that implements a saturating sigmoidal-like function by combining the nonlinear characteristics of NMOS and PMOS transistors. The circuit design is based on using a parameter sensitivity analysis to develop a robust design that will be relatively insensitive to process-parameter variations over the area of the die. The nonlinear resistor has been integrated into a module which realises a programmable digital synaptic weight capability. A neuron is effectively formed from the parallel interconnection that takes place as multiplier outputs are connected to create an input node to the resultant distributed neuron. Designs in 0.35 and 0.8 µm processes are compared with a conservative 1.2 µm CMOS implementation.

A 50-neuron CMOS analog chip with on-chip digital learning: design, development, and experiments

The model, implementation, and experimental application of a Dendro-dendritic Artificial Neural Network (DANN) with learning are presented. The DANN model lends itself to a direct all-MOS implementation. A learning algorithm is developed, then abstracted to a simple digital learning scheme. A 50-neuron analog chip with on-chip digital learning scheme is fabricated in 6800×4600 μm die size with 63,025 transistors and 1225 programmable synaptic weights in a standard 2 μ CMOS technology. Each synaptic weight is realized by a single (nonlinear) MOS transistor controlled via its gate-voltage. Two user-chosen analog gate-voltages are available to all synapses as two binary levels. The on-chip digital learning circuitry determines which binary level based on the desired patterns to be stored. Moreover, a synapse’s level can be assigned by the user or can be downloaded from an external source. Finally, we demonstrate the function of the chip, which is interfaced to a PC and augmented with graphical software, in three different experimental categories: (i) pattern recognition, (ii) edge detection, and (iii) as a locally connected network. The scalable architectural design and these three experimental categories show the chip’s versatile capabilities as a potential co-processor.

Programmable switched-capacitor neural network for MVDR beamforming

In this paper, a real-time adaptive antenna array based on a neural network approach is presented. Since an array operating in a nonstationary environment requires a programmable synaptic weight matrix for the neural network, the switched-capacitor (SC) circuits with the capability of programmability and reconfigurability is conducted to implement the neural-based adaptive array. Moreover, the SC techniques can directly implement the neural network with less chip area and provide the ratio of SC-equivalent resistors with accuracy of 0.1 percent. Programming of the switched-capacitor values could be made by allocating each synaptic weight to a set of parallel capacitors with values in a digitally programmable capacitor array (PCA). A relatively wide range of values (5 to 10 binary bits resolution) can be realized for each synaptic weight. A simulation tool called SWITCAP is used to verify the validity and performance of the proposed implementation. Experimental results show that the computation time of solving a linear array of 5 elements is about 0.1 ns for 1 ns time constant and is independent of signal power levels.

A programmable analog neural network processor

An analog neural network breadboard consisting of 256 neurons and 2048 programmable synaptic weights of 5 bits each is constructed and tested. The heart of the processor is an array of custom-programmable synapse (resistor) chips on a reconfigurable neuron board. The analog bandwidth of the system is 90 kHz. The breadboard is used to demonstrate the application of neural network learning to the problem of real-time adaptive mirror control. The processor control is 21 actuators of an adaptive mirror with a step-response setting time of 5 ms. The demonstration verified that it is possible to modify the control law of the high-speed analog loop using neural network training without stopping the control loop.