Programmable Low-pass Filter Research Articles

A programmable analog front-end with independent biasing technique for ECG signal acquisition

This paper presents a programmable low power and low noise analog front-end (AFE) for electrocardiogram (ECG) signal acquisition. A novel capacitor-coupled instrumentation amplifier (CCIA) features independent biasing technique and AC coupling to signal source is proposed. Independent biasing technique is capable of obtaining better noise performance and more stable static working point reducing the glitch of chopping. An AC coupling style helps suppress electrode DC offset and enhance input impedance with metal-oxide-metal capacitor array, which is symmetrical to the center to alleviate the mismatch of input capacitor enhancing system common mode rejection ratio (CMRR). The current steering technology (CST) and programmable feedback capacitors are utilized to achieve an area-efficient programmable low pass filter (PLPF) under PVT variations. Also, a charge buck after PLPF is introduced to strengthen the driving ability of AFE. To verify the proposed AFE structure, a prototype is designed in 0.13 μm standard CMOS process with a 1.2 V supply. Post-simulation results show that the input impedance reaches 1.4 GΩ under 50 Hz. The in-band white noise density and integrating noise are 48 nV/sqrt (Hz) and 0.6 μV, respectively. The obtained low pass corner of PLPF are 380 Hz, 451 Hz and 1 kHz. The CMRR and PSRR under montecarlo simulation are 93 dB and 77 dB, respectively. The power of whole AFE is 48 μW.

Analog Memristor-Based Dynamic Programmable Analog Filter

The memristor study now generally exhibit threshold voltage characteristics. The memristance changes when the voltage across the memristor is greater than the threshold voltage. Otherwise, the memristance is almost constant. Based on this feature, we design a general-purpose memristor programmable circuit that is simple to operate. In the field of communication and signal processing, programmable analog filters are required, and memristors with multi-valued characteristic are suitable as programmable impedance elements for such circuits. Through simulation and physics experiments, we demonstrate a memristor-based programmable low-pass filter using the designed programmable circuit to realize the dynamic adjustment of circuit parameters.

A Compensation Strategy of Flux Linkage Observer in SPMSM Sensorless Drives Based on Linear Extended State Observer

Flux linkage estimation based on the voltage model has been widely employed in surface-mounted permanent magnet synchronous machine (SPMSM) sensorless drives due to its simple implementation. To deal with dc-offset and dc-drift problems, the pure integrator is modified as a programmable low pass filter (LPF)in practice. However, the estimation accuracy of the rotor position is affected by the adopted filter. Although the position deviation is compensated in steady-state based on the frequency characteristics of the filter, the compensation effect deteriorates during a dynamic process which severely degrades the sensorless control performance. In order to effectively tackle this problem, a novel compensation strategy based on the linear extended state observer (LESO) is proposed in this paper. With the constructed LESO in the estimated synchronous rotating reference frame, the position estimation error can be detected and compensated both in the steady and dynamic state. Moreover, the observer is enhanced to improve the estimation accuracy in linear acceleration and deceleration. Finally, the feasibility of the proposed method is verified under various operating conditions with a 5.5 kW SPMSM drive system.

An Automatic Clock-Induced-Spurs Detector Based on Energy Detection for Direct Digital Frequency Synthesizer.

A clock-induced-spurs detector, composed of a programmable low-pass filter (LPF), energy detector and spur detection algorithm, is presented and applied to a four-channel 1 gigabit-samples-per-second (GSPS) direct digital frequency synthesizer (DDS). The proposed detector realizes the detection of spurs based on energy-detection, and the spur detection algorithm is adopted to automatically extract the amplitude and phase of clock-induced spurs, generated by the intermodulation of harmonic spurs and multiple clocks. Finally, the extracted features are sent to auxiliary DDS to decrease the target spur, following which the detector can be turned off to save power. Additionally, the detected characteristics under different output conditions can be read out through the interface for rapid frequency switching. The proposed detector integrated into a DDS is fabricated with a 65 nm complementary metal oxide semiconductor (CMOS) process and has an area of 190 μm × 320 μm. The measured power consumption is roughly 38 mW, consuming 6% that of a single-channel DDS. The test results show that the spurious-free dynamic range (SFDR) of this DDS can be successfully enhanced from −43.1 dBc to roughly −59.9 dBc without any off-chip instruments. This effectively proves that the detection accuracy of this detector can reach around −81 dBm.

Extended Digital Programmable Low-Pass Filter for Direct Noise Filtering of Three-Phase Variables in Low-Cost AC Drives

This paper proposes an extended structure of a programmable low-pass filter (PLPF) for direct filtering of three-phase variables in automotive AC drives. The PLPF adjusts its cut-off frequency according to the synchronous frequency of the AC motors. Moreover, it compensates gain attenuation and phase delay of the fundamental component signal. The conventional PLPF can only be applied to variables in the stationary reference frame. In order to obtain filtered three-phase variables, an inverse reference frame transformation is required. However, the extended structure, which includes reference frame transformations, can be directly applied to three-phase variables and remove the noise in the earlier stage before transformation. The extended PLPF is more useful for making signal flows clear and intuitive when organizing an algorithm that directly requires three-phase variables. The extended PLPF requires a moderate computational load corresponding with that of the conventional PLPF because its formula is simplified by use of Kirchhoff’s law. The reduction in the execution time is critical for implementing the filter based on low-cost microcontrollers. Using case studies, dead-time compensations and open-phase fault detection for AC drives show the effectiveness of the extended PLPF.

Carbon Nanotube Field Effect Transistors Based Digitally Reconfigurable Single Differential Voltage Current Conveyor based Analog Biquadratic Multifunctional Filter at 32nm Technology Node

Carbon Nanotube Field Effect Transistors (CNFET) are considered to be the potential candidates for overcoming the shortcomings associated with the scale of the art CMOS transistors; as the scaling continues. In this paper a digitally reconfigurable CNFET based biquadratic multifunctional filter employing a CNFET based single Differential Voltage Current Conveyor (DVCC) at 32nm technology node has been presented. The circuit utilizes a single CNFET based DVCC block along with the arrangement of few resistors and capacitors. The proposed digitally reconfigurable multifunctional filter circuit is able to obtain programmable low pass, high pass and band pass filter configurations using the same topology. The designed CNFET based multifunctional filter obtains a resonant frequency of the order of GHz. Furthermore, a 3-bit digital control of the designed multifunctional filter parameters i.e. Quality Factor (Qo) & resonant frequency has been made possible using the Current Summing Network (CSN). Sensitivity and comparative analysis has also been performed. The circuit has been simulated at a low voltage supply of 0.9V using HSPICE environment at 32nm technology node. The simulation results obtained are in sync with the theoretical analysis

Research on Improved Static Compensation Flux Error MARS Observer Based on SMC

Aiming at the integral drift and saturation problems of the traditional voltage model flux observer, an improved rotor flux observation scheme is proposed. A programmable low-pass filter is used to replace the pure integrator, and the flux error before the filter is corrected. The sliding mode speed controller is used to replace the traditional PI speed controller. The proposed observer can reduce the speed response overshoot of the system at medium and high speed range, reduce the steady-state time, and improve the load capacity and robustness of the system. The simulation results show the effectiveness of the algorithm.

A biasing based current mode analog front-end for biomedical applications

Abstract Electrocardiograms, Electromyogram, and Electroencephalogram, are very few extensions and low frequencies electronic detection system. An important part of their biomedical detection electronic system is the biopatensive props-device. In this article, analog front-end in a current mode has been proposed to bioptational signal acquisitions. It includes programmable profit-current (PGC) mode amplifier (MA) and 2nd current mode low-pass filter (CM-LPF). Amplifier operated and low-pass filter externally used ELIN circuits. EIN blocks were executed by the use of log-domain circuits. In the proposed circuit, a combination of pull up and pull down transistors which acts as an inverter is used for biasing purpose. The biasing is done in such a way that the transistors switch their region of operation between cutoff region and saturation region in order to perform switching action. The proposed current mode analog front-end consumes less material to implement circuit design.

A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process

A highly reconfigurable open-loop analog baseband circuitry with programmable gain, bandwidth and filter order are proposed for integrated linear frequency modulated continuous wave (LFMCW) radar receivers in this paper. This analog baseband chain allocates noise, gain and channel selection specifications to different stages, for the sake of noise and linearity tradeoffs, by introducing a multi-stage open-loop cascaded amplifier/filter topology. The topology includes a course gain tuning pre-amplifier, a folded Gilbert variable gain amplifier (VGA) with a symmetrical dB-linear voltage generator and a 10-bit R-2R DAC for fine gain tuning, a level shifter, a programmable Gm-C low pass filter, a DC offset cancellation circuit, two fixed gain amplifiers with bandwidth extension and a novel buffer amplifier with active peaking for testing purposes. The noise figure is reduced with the help of a low noise pre-amplifier stage, while the linearity is enhanced with a power-efficient buffer and a novel high linearity Gm-C filter. Specifically, the Gm-C filter improves its linearity specification with no increase in power consumption, thanks to an alteration of the trans-conductor/capacitor connection style, instead of pursuing high linearity but power-hungry class-AB trans-conductors. In addition, the logarithmic bandwidth tuning technique is adopted for capacitor array size minimization. The linear-in-dB and DAC gain control topology facilitates the analog baseband gain tuning accuracy and stability, which also provides an efficient access to digital baseband automatic gain control. The analog baseband chip is fabricated using 130-nm SiGe BiCMOS technology. With a power consumption of 5.9~8.8 mW, the implemented circuit achieves a tunable gain range of −30~27 dB (DAC linear gain step guaranteed), a programmable −3 dB bandwidth of 18/19/20/21/22/23/24/25 MHz, a filter order of 3/6 and a gain resolution of better than 0.07 dB.

A novel programmable attenuator based low Gm-OTA for biomedical applications

In this paper, a novel programmable operational transconductance amplifier (POTA) using a pseudo resistor based programmable attenuator is proposed. A 4th order Butterworth programmable low pass filter (LPF) targeted for biomedical applications is designed using the proposed POTA. The proposed POTA and the LPF are designed and implemented in 0.18 ​μm CMOS technology with a supply voltage of 1 ​V and their performances are evaluated through post-layout simulations. The proposed POTA consumes a power of 27 ​nW, and its transconductance could be varied from 27 ​nA/V to 75 ​nA/V. It has higher linearity, dynamic range (DR) of 85.62 ​dB–79.46 ​dB and lower input-referred noise (IRN) of 33.15 μVrms to 58.65 μVrms than pre-input voltage attenuator based OTAs. The proposed LPF consumes a power of 208 ​nW. Its output dynamic range and IM3 lie in the range of (62.1 ​dB–49.26 ​dB) and (61.87 ​dB–53.14 ​dB) respectively. Its cutoff frequency can be varied from 100 ​Hz to 250 ​Hz.

A novel dual loop adaptive equalizer based on spectrum balancing technique

Inductorless circuits are gaining advantage in RF and high-speed serial link circuits due to the reduced silicon area. This paper presents an inductor-less adaptive equalizer featuring both data rate adaptation and channel loss adaptation. The conventional adaptive equalizers use spectrum balancing technique. The spectrum balancing technique balances the power in low and high frequency components with cutoff frequency of the filters as 0.28Tb (Tb is the minimum bit period of the incoming data stream). The proposed technique removes the necessity of using high pass filter and uses only a programmable low-pass filter in the adaptive equalization loop. This technique leads to the tunability of the equalizer over a wide range of throughput and channel losses. For the proof of concept, the entire equalizer circuit is designed and fabricated in 180 nm mixed mode CMOS technology. The measurements with lossy channels show that the proposed adaptive equalizer is able to work well for the channel losses up to 6 dB and wide throughput of 1–3.125 Gbps. The design is targeted to operate at a maximum data rate of 3.125 Gbps to meet JESD 204 standards. The proposed adaptive equalizer consumes a power of 9.8 mW/Gbps including IO buffers.

A Fully Differential RC Calibrator for Accurate Cut-off Frequency of a Programmable Channel Selection Filter

A fully differential RC calibrator for accurate cut-off frequency of a programmable channel selection filter is proposed. The proposed RC calibrator consists of an RC timer, clock generator, synchronous counter, digital comparator, and control block. To verify the proposed RC calibrator, a six-order Chebyshev programmable low-pass filter with adjustable 3 dB cut-off frequency, which is controlled by the proposed RC calibrator, was implemented in a 0.18-mm CMOS technology. The channel selection filter with the proposed RC calibrator draws 1.8 mA from a 1.8 V supply voltage and the measured 3 dB cut-off frequencies of the channel selection LPF is controlled accurately by the RC calibrator.

Stationary Frame Induction Motor Feed Forward Current Controller With Back EMF Compensation

In this paper, a novel induction motor (IM) stator current controller is proposed based on the stationary frame feed forward controlling structure. The proposed regulator represents an improved variant of the existing stationary and rotational frame IM stator current regulators based on the back EMF compensation. The paper novelty consists of the stationary frame controlling structure based on two feed forward actions that enable asymptotic reference tracking. Namely, the novel stationary frame regulator includes a proportional integral (PI) regulation term combined with a stator resistance voltage drop and back EMF feed forward compensations, with the back EMF compensation based on the stator flux value estimated by means of a programmable low-pass filter. The feedback term is based on a PI controller, with the corresponding parameter tuning procedure outlined in the paper. The simulation runs are included in the paper in order to examine the regulator performance in relation to the factors critical to the IM stator current regulation: variable IM model parameter values, transport delay introduced in the control loop, variable stator frequency, and rotor speed values. Also, the experimental tests are presented and carried out on an experimental setup for different operating conditions typical for an IM drive.

Improved Stator Flux Estimator for Speed Sensorless Induction Motor Drives

In this paper, an improved induction motor (IM) stator flux estimation method is proposed, based on a novel integrator scheme with a closed-loop dc offset compensation algorithm. When compared with the existing stator flux estimators, the proposed solution represents an improved programmable low-pass filter. Namely, by introducing a novel closed-loop dc offset compensation structure, two major drawbacks of existing stator flux estimators are overcome; their stability and accuracy at low frequencies, and the estimator response time over the whole frequency range, introducing an estimation algorithm much simpler than existing solutions. The performance of the novel stator flux estimator is tested by means of simulation runs and experimental tests, with the proposed algorithm used for the estimation of the stator flux, rotor flux, and rotor speed in a direct field-oriented controlled IM control algorithm. The simulations and experimental results show that the proposed estimator enables accurate and stable operation under all operating conditions, including the critical low stator frequency range.

An Improved Flux Estimator for Gap Flux Orientation Control of DC-Excited Synchronous Machines

Flux estimation is a significant foundation of high-performance control for DC-excited synchronous motor. For almost all flux estimators, such as the flux estimator based on phase locked loop (PLL), DC drift causes fluctuations in flux magnitude. Furthermore, significant dynamic error may be introduced at transient conditions. To overcome these problems, this paper proposes an improved flux estimator for the PLL-based algorithm. Filters based on the generalized integrator are used to avoid flux fluctuation problems caused by the DC drift at the back electromotive force. Programmable low-pass filters are employed to improve the dynamic performance of the flux estimator, and the cutoff frequency of the filter is determined by the dynamic factor. The algorithm is verified by a 960V/1.6MW industrial prototype. Simulation and experimental results show that the proposed estimator can estimate the flux more accurately than the PLL-based algorithm in a cycloconverter-fed DC-excited synchronous machine vector control system.

Realization of Programmable Analog Circuits with Digital Potentiometer

This paper introduced the structure and special property with type device, analyzed how to realized programmable analogue function module with digital potentiometer. This paper gave a design example of programmable second-order active low pass filter by using digital potentiometer. The programmable filter can be application to the signal filter processing of data acquisition systems. This paper has reference value of theory and practice on the application of digital potentiometer

자동차 전동 시스템을 위한 Programmable 저역 통과 필터 기반의 상전류 극성 판단 및 데드타임 보상

Abstract : This paper proposes a dead time compensation method for an AC motor drive using phase current polarity information which is detected based on a digital programmable low-pass filter (PLPF). The polarity detection using the PLPF is an alternative solution of a conventional method which uses a general low-pass filter (LPF) and hysteresis bands in order to avoid jittering due to noises. The PLPF not only adjusts its cutoff frequency according to the synchronous frequency of AC motors but also eliminates a gain attenuation and phase delay which are main problems of the general LPF. Through the PLPF, a fundamental component signal without gain and phase distortions is extracted from the measured raw current signal with noise. By use of the fundamental component, the polarity of current is effectively detected by reducing the hysteresis band. Finally, the proposed method compensates the dead time effects by adding or subtracting average voltage value to voltage references of the controller according to the detected current polarity infor-mation. The proposed compensation method is experimentally verified by compared with the conventional method.

BLDC 고속 센서리스 구동의 ZCP 추정 오차 저감을 위한 Programmable Low Pass Filter 설계

This paper presents a design method of programmable low pass filter(PLPF) which reduce an estimation error of a zero crossing point(ZCP) for a high speed brushless DC(BLDC) motor drive. BLDC motor sensorless drive is possible by estimation of ZCP. The ZCP estimated by detecting a change of back-EMF polarity has the estimation error because noises exist on the measured back-EMF. Therefore a calculated commutation timing using the ZCP is inaccurate. And the inexact commutation timing leads to ripples of 3-phase current and degradation of drive performance. This paper proposes the design method of the PLPF to overcome these problems. First, a speed calculated a inaccurate period of the ZCP is analyzed in the frequency domain. Then, the PLPF that has varying cut-off frequency according to change of the speed is designed on the frequency analysis result. The proposed method is verified by the experiment.

A Bio-Inspired APS for Selective Visual Attention

This letter presents an active pixel sensor architecture that mimics the eye adaptive behavior through dynamic background subtraction as a basis for image interpretation tasks. The pixel extracts temporal contrast as a low-level visual feature for successive high-level processing targeted to monitoring applications. To do this, each pixel compares the acquired value with a voltage range computed over the past pixel behavior; values outside this range signal a potential alert. Two switched-capacitor programmable low-pass filters are embedded. The 26 μm, 12% fill-factor, fully functional 45 T pixel has been fabricated in a 0.35 μm CMOS technology.

A Versatile Rotor Position Computation Algorithm for the Power Control of a Grid-Connected Doubly Fed Induction Generator

This paper proposes a simple yet versatile rotor position computation algorithm (RPCA) for the rotor position and speed of a doubly fed induction machine. The rotor position is computed in a straightforward manner obviating the need for estimation. The resolved components of stator flux vector are computed using measurable stator and rotor quantities. Although it is an open-loop technique, it does not involve integration, recursive techniques, recomputations or programmable low-pass filters, etc. Starting on the fly, accurate computation near and through the synchronous speed, immunity against fluctuations in the grid voltage, and frequency are the other advantages of the algorithm. Reduced complexity and the computational burden facilitate the easy implementation of the algorithm on a low-cost fixed-point processor. Furthermore, unlike most techniques reported so far, there is no need to assume a constant stator flux since the algorithm is versatile to allow for variations in the grid or stator flux. For the purpose of verification, the proposed RPCA, employed in decoupled power control, is implemented for the laboratory test bench with a 3-hp doubly fed induction generator (grid-connected) system and a TMS320LF2407A DSP controller. The efficacy of the algorithm is demonstrated through the extensive experimental results. Overall, the very encouraging results endorse the proposed algorithm.