Programmable Logic Device Research Articles

Thermal characterization methodologies for experimental minichannel heat sink designs in printed circuit board assemblies

There has been a growing demand for novel, highly efficient, power-saving cooling solutions in recent years. In many cases, standard cooling techniques offer only limited opportunities to prevent the overheating of circuits. Such issues concern high-speed Printed Circuit Board Assemblies (PCBA) in data centers and telecommunication racks, where the flow of the cooling medium is obstructed due to the lack of space. Size limitations can also be a serious problem when cooling high-power devices because the devices consume a large space. Since the heat sink-based cooling solutions and the sophisticated IC packages only deal with one possible heat flow path, we were given the idea of enhancing the secondary heat flow path towards the Printed Circuit Board (PCB). Led by this intention, the idea of creating an embedded minichannel system inside the circuit board and circulating the cooling agent was realized. Through this method, we could decrease the board-to-ambient thermal resistance significantly. This paper presents the demonstration and feasibility study of this method. One of the main aims of this study is to demonstrate the applicability of the proposed concept in PCBAs, where the primary concerns are the low-cost manufacturability and available space. The other goal is to create an adaptation of the standard thermal characterization methodologies to deal with the specific dissipating components in the PCBA demonstrators. In the first part, the manufacturing technology is elaborated on, and its efficiency is characterized by thermal transient testing and Computational Fluid Dynamics (CFD) simulations. For these use cases, it was noted that the cumulative thermal resistance decreased by approximately 60 % when a volumetric flow rate of 100 ccm was applied in the minichannels. In the second part, a more sophisticated technology demonstration is realized and characterized by adding the proposed embedded minichannel heat sink to an existing high-speed PCBA. A specific thermal transient testing was implemented specifically for this use case, and it was carried out on programmable logic devices by utilizing general-purpose programmable logic to construct the necessary measurement methods. In the future, this feature can be used in different logic circuit designs where it is not possible to determine the junction temperature directly.

Аналіз застосування технологій ПЛІС в складі IoT

The subject of study in this article and work is the modern technologies of programmable logic devices (PLD) classified as FPGA, and the peculiarities of its application in Internet-of-Things domain at different architectural layers of the implementation, as well as the elements of decision making during choosing of appropriate solutions based on FPGA in the context of implementation of IoT tasks with the requirements of intensive computations. The goal is to analyze the possibilities and peculiarities of the application of technology of programmable logic devices as part of the modern architecture of the Internet of Things with the improvement of decision making process during the choosing of appropriate technical solutions for the use of FPGA with taking into account the types of tasks. Tasks: to analyze the current state of demands regarding the use of FPGA technology in IoT projects; to analyze the challenges and limitations for the application of FPGA technology at different layers during the prototyping of IoT infrastructure; to propose ways of the use of FPGA technology in the IoT infrastructure with the use of high-speed computations; to analyze the advantages and disadvantages of the proposed approaches of integration of FPGA technology; to provide recommendations and determine the further direction of the research of the use of FPGA technology as a part of the IoT infrastructure considering of AI/ML tasks; to provide a practical example of the use of FPGA technology during the creation of a high-performance IoT system. According to the tasks, the following results were obtained. The analysis of the current state of the use of FPGA technology in IoT projects is performed, that showed the significant potential of these technologies for the implementation of high-speed computations in Internet of Things systems. A classification of the ways of applying FPGA in the tasks of real-time data processing and implementation of neural networks is proposed. The set of limitations of the possibility of FPGA technology applying at different layers of IoT infrastructure is defined. It includes high equipment costs, the need for specific design skills, limitations in energy consumption, and the complexity of the integration with existing systems. The practical example of the use of the IoT system with the implementation of high-intensive computations is provided. Conclusions. The main contribution and scientific novelty of the obtained results is that the conducted analysis allows to make a decision about the possibility of applying programmable logic in the construction of IoT projects and home automation systems. Based on the proposed classification of types of IoT tasks, there is a possibility of making a decision on the application of FPGA technology as a separate integrated circuit in the system or using a complete instance of FPGA as a Service in the cloud environment.

A hardware architecture for single and multiple ellipse detection using genetic algorithms and high-level synthesis tools

Ellipse detection techniques are often developed and validated in software environments, neglecting the critical consideration of computational efficiency and resource constraints prevalent in embedded systems. Furthermore, programmable logic devices, notably Field Programmable Gate Arrays (FPGAs), have emerged as indispensable assets for enhancing performance and expediting various processing applications. In the realm of computational efficiency, hardware implementations have the flexibility to tailor the required arithmetic for various applications using fixed-point representation. This approach enables faster computations while upholding adequate accuracy, resulting in reduced resource and energy consumption compared to software applications that rely on higher clock speeds, which often lead to increased resource and energy consumption. Additionally, hardware solutions provide portability and are suitable for resource-constrained and battery-powered applications. This study introduces a novel hardware architecture in the form of an intellectual property core that harnesses the capabilities of a genetic algorithm to detect single and multi ellipses in digital images. In general, genetic algorithms have been demonstrated to be an alternative that shows better results than those based on traditional methods such as the Hough Transform and Random Sample Consensus, particularly in terms of accuracy, flexibility, and robustness. Our genetic algorithm randomly takes five edge points as parameters from the image tested, creating an individual treated as a potential candidate ellipse. The fitness evaluation function determines whether the candidate ellipse truly exists in the image space. The core is designed using Vitis High-Level Synthesis (HLS), a powerful tool that converts C or C＋＋functions into Register-Transfer Level (RTL) code, including VHDL and Verilog. The implementation and testing of the ellipse detection system were carried out on the PYNQ-Z1, a cost-effective development board housing the Xilinx Zynq-7000 System-on-Chip (SoC). PYNQ, an open-source framework, seamlessly integrates programmable logic with a dual-core ARM Cortex-A9 processor, offering the flexibility of Python programming for the onboard SoC processor. The experimental results, based on synthetic and real images, some of them with the presence of noise processed by the developed ellipse detection system, highlight the intellectual property core’s exceptional suitability for resource-constrained embedded systems. Notably, it achieves remarkable performance and accuracy rates, consistently exceeding 99% in most cases. This research aims to contribute to the advancement of hardware-accelerated ellipse detection, catering to the demanding requirements of real-time applications while minimizing resource consumption.

Realization of logic operations via spin–orbit torque driven perpendicular magnetization switching in a heavy metal/ferrimagnet bilayer

Programmable and non-volatile spin-based logic devices have attracted significant interest for use in logic circuits. Realization of logic operations via spin–orbit torque (SOT) driven magnetization switching could be a crucial step in the direction of building logic-in-memory architectures. In this work, we demonstrate experimentally, the realization of four logic operations in a heavy metal/ferrimagnet bilayer structure via SOT switching. We also propose a general scheme for choosing input parameters to achieve programmable logic operations. The bulk and tunable perpendicular magnetic anisotropy and relatively lower saturation magnetization in ferrimagnets are found to make them more energy efficient in performing logic operations, as compared to conventional ferromagnets. Thus, ferrimagnets are promising candidates for use in logic-in-memory architectures, leading to the realization of user-friendly spin logic devices in the future.

A grid-connected eleven-level power conversion interface

ABSTRACT This paper proposes a grid-connected eleven-level power conversion interface (GCELPCI) for renewable power systems. The proposed GCELPCI is composed of a four-port DC-DC power converter (FPDDPC) and an eleven-level inverter (ELI). The FPDDPC combines a boost power converter and a transformer with a turn ratio of 2:1 to generate multiple combinations of the output voltages for the DC bus voltage of the ELI. The ELI integrates an asymmetric voltage technique on a T-type inverter to further convert the DC output voltages of FPDDPC into eleven-level AC voltage. A sinusoidal current is generated by the proposed GCELPCI through the filter inductor and injected into the power grid. Only nine power electronic switches are used in the ELI to generate an eleven-level AC voltage, the number of power electronic switches is reduced to simplify the power circuit. In addition, the capacity of the filter inductor is reduced. A digital signal processor (DSP) and a complex programmable logic device (CPLD) chip are used as the digital controller to complete a hardware prototype to verify the performance of the proposed GCELI.

A logic device based on memristor-diode crossbar and CMOS periphery as spike router for hardware neural network

A programmable logic device based on a memristor-diode crossbar and CMOS logic has been developed. The crossbar implements NAND logic gates using memristor ratioed logic and CMOS inverters. The digitally controlled peripheral circuit provides digital signals transmission and allows modification and evaluation memristor states in the crossbar. The proposed logic device circuit requires fewer transistors than known analogues and less area on the chip.The maximum size of the crossbar in a logic device is estimated by numerical simulation at the level of electrical circuits. The limited size is caused by the degradation of the logic levels voltages in the memristor-diode crossbar. The operability of peripheral circuits as part of a complete electrical circuit of a logic device is demonstrated during the simulation of the execution of logical operations, the processes of modification and evaluation states of individual memristors.

Implementation of EnDat Interface Master Using Configurable Logic Block in MCU

In this study, we propose an implementation method of the Encoder Data (EnDat) interface master for slave encoders using only a configurable logic block (CLB) and a serial peripheral interface (SPI) integrated into microcontroller units. By programming the CLB device to execute logic functions and finite state machines designed for the EnDat interface master operation, we realize the EnDat and SPI clocks that are required for the EnDat interface master operation. This approach is cost-efficient because additional hardware components, such as a field-programmable gate array or a complex programmable logic device, are unnecessary for the master implementation. We build a one-axis feed drive system that is powered by an AC motor and equipped with an EnDat linear encoder for measuring table speed and position. By performing various experiments for table position and speed control based on the built feed drive system, we verify the performance and practical usefulness of the implemented EnDat interface master. The maximum EnDat clock frequency without the propagation delay compensation is achieved by 2 MHz, which can cope with 16 kHz control cycle frequency. The usefulness is demonstrated by showing the table speed and position control performance that are acceptable in real applications.

Simulation and FPGA based Implementation of PI and Fuzzy Controllers for Cascaded Asymmetric Multilevel Inverter

The main objective of this work is to improve the performance of Multilevel Inverter by using the novel LS-PD- PWM and controlling technique instead of the existing approach. The proposed work focus on closed loop controller such as existing PI and Fuzzy Logic Controller for resistive load with Multilevel Inverter. The proposed Asymmetric fifteen level Inverter offers less THD and high frequency than the Asymmetric nine level inverter. Asymmetric multilevel inverter is used to reduce the switching losses and THD. In this work is the generation and implementation of Pulse Width Modulation (PWM) techniques using Field Programmable Gate Array (FPGA) for Multilevel Inverter. PWM can be generated via Microprocessors, Microcontroller, FPGA and DSP Processors. Higher density Programmable Logic Devices (PLD) such as FPGAs can be used to amalgamate large amounts of logic into a single Integrated. Pulse width modulation (PWM) is generally used in power converter control. To generate LS-PD- PWM by using FPGA, this occupies less memory capacity and accurate than conventional one. An efficient PWM generation technique is performed using FPGA for lower frequency applications. Simulation and synthesis is done by ModelSim6.3c and Xilinx10.1. Further, the Implementation is carried out by FPGA Spartan3 Xc3s50. Key Word: PWM, FPGA, PLD (Programmable Logic Devices), LS-PD-PWM

Modeling of binary-coded decimal to seven segment display decoder using silicon microring resonator-based programmable logic device

Modeling of binary-coded decimal to seven segment display decoder using silicon microring resonator-based programmable logic device

Testing and Delay-Monitoring for the High Reliability of Memory-Based Programmable Logic Device

Testing and Delay-Monitoring for the High Reliability of Memory-Based Programmable Logic Device

TEST GRAPH-SCHEMES OF THE ALGORITHMS OF FINITE STATE MACHINES WORK FOR ASSESSING THE EFFICIENCY OF AUTOMATED SYNTHESIS IN XILINX VIVADO CAD

Context. The problem of evaluating the effectiveness of the automated design of a microprogram finite state machine with the operational transformation of state codes using Xilinx Vivado CAD is considered. The object of the research was graph-schemes of control algorithms implemented by finite state machine and able to prove the effectiveness of the principle of operational transformation of state codes in comparison with standard synthesis methods built into the CAD, in the context of hardware expenses optimization.
 Objective. Development and research of graph-schemes of control algorithms in order to substantiate the effectiveness of the application of structure of the finite state machine with datapath of transitions in comparison with the built-in methods of synthesizing finite state machines in Xilinx Vivado CAD in the basis of programmable logic devices.
 Method. The research is based on the hypothetical assumption that the Xilinx Vivado CAD has built-in methods of automated design of the circuit of a finite state machine, the effectiveness of which, according to the criterion of hardware expenses, exceeds other known methods of optimizing hardware expenses in the finite state machine circuit. In order to refute this hypothesis, it is proposed to prove that in some cases known methods of hardware expenses optimization in the finite state machine circuit are more effective in comparison with the methods built into CAD. In this work, as a well-known optimization method, the method of operational transformation of state codes, which corresponds to the structure of a finite state machine with datapath of transitions, is chosen. The effectiveness of this method is demonstrated on the example of several test graph-schemes of algorithms, the structure of which is abstract and artificially adapted to the chosen optimization method. The adaptation of the selected graph-schemes of the algorithms consists in the fact that a relatively small number of transition operations is required for their implementation with the help of a finite state machine with datapath of transitions. This contributes to the simplification of the circuit of the finite state machine and the reduction of hardware costs for its implementation. At the same time, the test graph-schemes of the algorithms have the possibility of scaling, which allows to automate the construction of VHDL models of the corresponding finite state machines for graph-schemes of different sizes and to evaluate the optimization of hardware expenses for finite state machines of different complexity.
 Results. Using the example of several graph-schemes of algorithms, it is demonstrated that in some cases none of the finite state machine synthesis methods built into the Xilinx Vivado CAD is able to surpass the method of operational transformation of state codes according to the criterion of hardware expenses for the implementation of a finite state machine circuit. At the same time, a several-fold gain in hardware expenses can be achieved, which indicates the expediency of using this method under certain conditions. The formal definition of such conditions for the considered and other known optimization methods is a separate unsolved scientific problem.
 Conclusions. The conducted experiments confirmed that in some cases, the known methods of synthesis of finite state machines allow to obtain circuits with lower hardware expenses than when using the methods of synthesis of finite state machines contained in Xilinx Vivado CAD. This testifies to the general expediency of using existing and developing new methods of hardware expenses optimization in the circuit of the finite state machines and the current relevance of the theory of the synthesis of digital automata as a scientific direction.

Метод створення і впровадження FPGA проєктів стійких до змін вимог і середовищ розроблення для хмарних інфраструктур

The subject of study in this article is the modern technologies of programmable logic devices, the history of product changes of leading manufacturers, including development environments, and project optimization processes. The goal is to improve modern methods, technologies, and software tools for the development and integration of FPGA-as-a-Service in the form of services in cloud infrastructures, data centers, and on-board high-performance systems, with taking into account the ever-changing conditions and requirements, and the constraints of platforms. Task: to analyze the history of product changes of the leading vendors and manufacturers of programmable logic devices; analyze the dynamics of changes in the functionality of project development environments for FPGA-based systems, with taking into account the existing requirements and restrictions from vendors of software and hardware platforms and components; perform a comparative analysis of modern development boards and accelerator cards for the prototyping and testing of projects based on the chips of programmable logic; analyze the use of an existing services and solutions based on FPGA technologies as part of cloud services from modern cloud providers; propose practical steps for the development of systems based on FPGA resistant to project requirements change; propose the sequence for the development and optimization of high-performance systems with their implementation based on FPGA; and to provide practical example of the use of the proposed method. According to the tasks, the following results were obtained. The history of changes in the leading companies of programmable logic manufacturers, as well as changes in versions of the development environments and the products of one of the largest companies, is analyzed. The use of existing FPGA-based solutions as part of cloud services is analyzed in detail. Two sequences for optimizing projects and increasing their productivity with reducing of the prototyping efforts during their creation and porting to new versions of software and hardware platforms are provided. Based on the results of the research, a prototype was developed and tested, which allowed the application of the proposed method in practice for adapting and porting the FPGA as a service project during the transfer to another version of the accelerator card. Conclusions. The main contribution and scientific novelty of the obtained results is that an experimental study of the paradigm of runtime reprogramming of programmable logic was performed, which made it possible to formulate the elements of a new method of creation projects as a service for cloud infrastructures, data centers, and artificial intelligence systems. A set of practical steps for the development of systems that are tolerant to changes in conditions and requirements is proposed. The application of the proposed method allows to avoid costs of project support in the case of changes in requirements.

All-optical generation of static electric field in a single metal-semiconductor nanoantenna

Electric field is a powerful instrument in nanoscale engineering, providing wide functionalities for control in various optical and solid-state nanodevices. The development of a single optically resonant nanostructure operating with a charge-induced electrical field is challenging, but it could be extremely useful for novel nanophotonic horizons. Here, we show a resonant metal-semiconductor nanostructure with a static electric field created at the interface between its components by charge carriers generated via femtosecond laser irradiation. We study this field experimentally, probing it by second-harmonic generation signal, which, in our system, is time-dependent and has a non-quadratic signal/excitation power dependence. The developed numerical models reveal the influence of the optically induced static electric field on the second harmonic generation signal. We also show how metal work function and silicon surface defect density for different charge carrier concentrations affect the formation of this field. We estimate the value of optically-generated static electric field in this nanoantenna to achieve ≈108V/m. These findings pave the way for the creation of nanoantenna-based optical memory, programmable logic and neuromorphic devices.

Charge Couple Device (CCD) Photoelectric Signal Data Acquisition and Its Application in the Machine Vision of Artificial Intelligence

The development of Charge Couple Device (CCD) technology is particularly rapid in the fields of image sensors and non-contact measurement. In this study, a data acquisition device applied to CCD photoelectric detection system is designed. Among them, the design of the Differential Amplification (DA) module, Analog-to-Digital Converter (ADC) module, First In First Out (FIFO) cache module, and Complex Programmable Logic Device (CPLD) module in this device are emphasized. The ADC circuit in the ADC module converts two 4 MHz analog photoelectric signals generated by the CCD sensor at a frequency of 8 MHz, and then outputs 12-bit digital signals. The collected photoelectric signal is used to detect the damage to the surface of ancient buildings with the machine vision technology of artificial intelligence (AI). In the test, the DA circuit can adjust the voltage range of two photoelectric analog signals output by CCD to a predetermined range (1.5 V∼2.0 V). In the ADC circuit test, there is no data in the FIFO when there is no input conversion, and the converted data will be stored in the internal FIFO during the conversion clock period. Based on machine vision technology, surface damage types of ancient buildings are defined, namely spalling, cracks, and disruption, and surface image samples are generated from collected signals. The samples are trained using the convolutional neural network, and the classifier is generated. The test reveals that the designed photoelectric signal acquisition device and AI machine vision technology can accurately classify the surface damage of ancient buildings.

An Ultrathin Flexible Programmable Spin Logic Device Based on Spin–Orbit Torque

Flexible electronic devices have shown increasingly promising value facilitating our daily lives. However, flexible spintronic devices remain in their infancy. Here, this research demonstrates a type of nonvolatile, low power dissipation, and programmable flexible spin logic device, which is based on the spin-orbit torque in polyimide (PI)/Ta/Pt/Co/Pt heterostructures fabricated via capillary-assisted electrochemical delamination. The magnetization switching ratio is shown to be about 50% for the flexible device and does not change after 100 cycles of bending, indicating the device has stable performance. By designing the path of pulse current, five Boolean logic gates AND, NAND, NOT, NOR, and OR can be realized in an integrated two-element device. Moreover, such peeling-off devices can be successfully transferred to almost any substrate, such as paper and human skin, and maintain high performance. The flexible PI/Ta/Pt/Co/Pt spin logic device serves as logic-in-memory architecture and can be used in wearable electronics.

Universal verification methodology-based airborne electronic hardware certification approach for ARINC-429

PurposeThe purpose of this paper is to present a verification methodology for custom micro coded components designed for Avionics projects. Every electronic hardware which will be developed for an aircraft must be designed with the compliance of DO-254 processes. Requirements are the key elements of the aviation. All the requirements must be covered by the design to be considered as completed. Therefore, verification of the custom micro coded components against requirements should be comprehensively addressed. The verification using the manual testing approach is less preferable, as humans can possibly make mistakes. Therefore, the most used verification method today is the automated simulation.Design/methodology/approachThe industry has developed a common methodology for generating automated testbenches by following the standardized guideline. This methodology is named as the universal verification methodology (UVM). In this paper, the verification study of ARINC-429 data bus digital design is presented to describe the DO-254 verification process using the UVM.FindingsThe results are supported with functional coverage and code coverage in addition to the assertions. It is observed that the design worked correctly.Originality/valueTo the best of the authors’ knowledge, this is the first study comprehensively describing the DO-254 verification process and demonstrating it by the UVM application of ARINC-429 on programmable logic devices.

Tunable Multilevel Gate Oxide Capacitance and Flat‐Band Voltage Shift Characteristics by Filament Formation in Double‐Floating‐Gate Metal–Oxide–Semiconductor Capacitors (Adv. Electron. Mater. 4/2023)

Metal–Oxide–Semiconductors In article number 2201110 by Tae-Sik Yoon and coworkers, a tunable multilevel gate oxide capacitance and flat-band voltage shift characteristics in double-floating-gate metal-oxidesemiconductor capacitors are demonstrated as operating with both conducting filament formation and electrical charging in the gate stack, depending on the constituent materials and device geometries. It paves the way for the potential application to non-volatile memory and programmable logic devices.

Programmable skyrmion-based logic gates in a single nanotrack

Programmable logic devices with multiple functions are key ingredients in information technology. Here we propose a multifunction logic device based on the current-driven skyrmion motion in a single nanotrack, where the spatially modulated Dzyaloshinskii-Moriya interaction introduces a potential barrier to the skyrmion. Three stable stages of the skyrmion location under a driving current of different magnitudes are demonstrated at room temperature through micromagnetic simulations, according to which we implement all necessary logic gates for computing applications. Our proposal provides a feasible scheme to design skyrmion-based programmable logic devices.

CLB-Based Development of BiSS-C Interface Master for Motor Encoders

Encoder interfaces should be operated in real time with high precision and fast processing for industrial motor control systems. The continuous bidirectional serial synchronous (BiSS-C) interface is an open-source serial communication protocol designed for motor encoders and is suitable for industrial purposes because of its fast serial communication speed. In this study, we propose a method for developing a BiSS-C interface master for a motor encoder slave, using only the configurable logic block (CLB) peripheral integrated into TI microcontroller units. By analyzing the detailed operation protocol of the BiSS-C interface, we create the truth and state tables for logic circuits and finite state machines, which are required for the BiSS-C interface master. Then, by programming the CLB based on the created truth and state tables, we implement the master clock, serial peripheral interface (SPI) clock, and operational process for the master. This approach is cost-efficient because additional hardware components, such as a field-programmable gate array or a complex programmable logic device, are not required for the master implementations. The developed method can be immediately applied to developing the masters for other BiSS-C encoders with different specifications, which is certainly necessary for a motor drive development and test. By building an AC motor control system with the developed master and performing various experiments, we verify the performance and practical usefulness of the developed BiSS-C interface master. The maximum master clock frequency without any CRC errors is achieved by 6.25 MHz, which can cope with more than 20 kHz motor control cycle frequency. The usefulness is demonstrated by showing the motor speed and position control performance that are acceptable in real applications.

Tunable Multilevel Gate Oxide Capacitance and Flat‐Band Voltage Shift Characteristics by Filament Formation in Double‐Floating‐Gate Metal–Oxide–Semiconductor Capacitors

AbstractTunable multilevel gate oxide capacitance and flat‐band voltage shift characteristics in double‐floating‐gate metal–oxide–semiconductor (DFG‐MOS) capacitors are investigated for non‐volatile memory and programmable logic device applications. The DFG‐MOS capacitor with the structure of Ag(control gate)/CeO2(upper control oxide)/Al(upper FG)/CeO2(lower control oxide)/Pt(lower FG)/HfO2(tunneling oxide) on n‐Si substrate, that is Ag/CeO2/Al/CeO2/Pt/HfO2/n‐Si, exhibits three capacitance states as a result of reversible formation and rupture of conducting filaments at serially stacked Ag/CeO2/Al and Al/CeO2/Pt capacitors upon applying positive and negative gate voltages, respectively. In contrast, the DFG‐MOS capacitor with Ag/CeO2/Pt/HfO2/Pt/HfO2/n‐Si employing inert Pt upper and lower FGs exhibits two capacitance states via the formation and rupture of filament only at the upper Ag/CeO2/Pt stack. Instead, it accompanies a flat‐band voltage shift by electrical charging at the lower FG of Pt. The proposed devices operate with tunable multilevel gate oxide capacitance and flat‐band voltage shift associated with filament formation inside gate stacks and electrical charging with respect to the constituent materials of the FGs. These results pave the way for potential application to non‐volatile memory and programmable MOSFET logic device with tunable gate oxide capacitance, without relying solely on the electrical charging used in the current flash‐type memory.