Programmable Logic Array Structure Research Articles

Application of Generalized Reed–Muller Expression for Development of Non-Binary Circuits

Semiconductor devices and binary information technology reach their limits set by the atomic size of miniaturization, calculation speed, and the fundamental principle of energy dissipation per bit processing. Therefore, new technologies in logic design and mathematical approaches must be investigated. Application of multiple-valued logic (MVL) in logic design allows developing gates and circuits with more than two stable states. This enables packing an unprecedented high-density of information. Based on this idea, a new technique of the programmable logic arrays (PLA) construction based on MVL units is considered. The unique aspect of this technique is the application of recurrent generalized Reed–Muller expression (GRME) for MVL function representation. The recurrent procedure for this expression’s construction is considered and applied in the PLA development. The proposed structure of PLA consists of two blocks that are memory and logic block. In this paper, we also consider the possibility to use the ferroelectrics for the implementation of cells of the memory block of PLA. The development of gates with multi-stable states is possible by the ferroelectrics ability to pin the polarization as a sequence of stable states.

Programmable synthesis of multi-valued multi-threshold functions for implementation using charge-coupled devices

The use of programmable logic array structures for the implementation of multi-valued multi-threshold (MVMT) functions using charge-coupled device technology is considered. Two new such structures for the implementation of MVMT functions are introduced. The number of functions realized using these structures is shown to be larger than those realized using previously proposed structures. The new structures are dynamically reprogrammable at the user level by controlling the thresholds of the gates used. One of the proposed structures is superior to the other in terms of the number of functions realized per one column. However, this increase in functionality is achieved at the expense of increasing the number of gates per column by 50%.

Programmable logic array structure for realization of multi-valued multi-threshold functions using charge-coupled devices

Programmable logic array (PLA) structures are investigated for the implementation of multi-valued multi-threshold functions using charge-coupled device technology. A new PLA structure is introduced for this purpose. It is shown that the number of functions realized using this structure is larger than those realized using an existing PLA structure. The new structure exhibits the desirable feature of being dynamically reprogrammable at the user level by controlling the thresholds of the gates used.

A low-power PLA for a signal processor

A standard fast programmable logic array (PLA) structure is discussed, with emphasis on its power consumption drawbacks. An exploration of alternatives to this structure leads to a presentation of the architecture and design of a low-power PLA structure used in a digital signal processing (DSP) environment. This PLA achieves low power consumption by a combination of pipelining, use of a NAND-OR configuration, and a simplified addressing scheme. Experimental results for the temperature range of 0 to 70 degrees C indicate that the circuit works as expected in a range extending to at least 3.5 V. >

A Heuristic Test-Pattern Generator for Programmable Logic Arrays

This paper describes a heuristic method for generating test patterns for Programmable Logic Arrays (PLAs). Exploiting the regular structure of PLAs, both random and deterministic test-pattern generation techniques are combined to achieve coverage of crosspoint defects. Patterns to select or deselect product terms are generated through direct inspection of an array; test paths to an observable output are established by successive, rapidly converging assignments of primary input values. Results obtained with a PL/I program implementation of the method are described; these results demonstrate that the method developed is both effective and computationally inexpensive.

Design Automation and the Programmable Logic Array Macro

The Programmable Logic Array (PLA) macro is a physical structure which simplifies LSI chip design while yielding high density and good performance. In addition, the inherent order and regularity of this structure provide opportunities to speed design through automated logic documentation, design verification by computer simulation, and computer-automated physical design. In this paper a chip design methodology is described which is based on the use of PLA structures (or macros) within a chip. Logic functions in array form are specified in a compact notation that is automatically converted either to array personalization patterns or to conventional logic blocks for input to existing checking and testing software. Simulation of any logic array is performed by a single program subroutine operating on these patterns. In addition, the simple, regular nature of the logic array lends itself to automatic generation of the layout geometries necessary to actually build the array on a silicon chip. Programs developed for these purposes and the PLA macro design procedures are described in the context of an engineering design system.

An Examination of the Cost Function for Programmable Logic Arrays

Cost functions for combinational switching circuits are commonly defined as monotonically increasing functions of the number of gates and the number of inputs. The structure of programmable logic arrays (PLA's) is such that the cost is more aptly only dependent on gate quantity. The consequences of redefining cost for PLA's are studied with respect to covering algorithms. The major benefits are that a multiple output prime implicant (implicate) table can be viewed as a single output table and that minimal covers can be determined much more simply, especially for cyclic tables.

Modified programmable logic array with more product terms

Some simple modifications to the basic programmable logicarray structure are described which result in an increase in the number of product terms available. Provided the degree of modification is small, then a worthwhile increase in the number of product terms is obtained with little disadvantage.