Programmable Logic Applications Research Articles

Photoelectric performance of InSe vdW semi-floating gate p–n junction transistor

Semi-floating gate transistors based on vdW materials are often used in memory and programmable logic applications. In this paper, we propose a semi-floating gate photoelectric p–n junction transistor structure which is stacked by InSe/h-BN/Gr. By modulating gate voltage, InSe can be presented as N-type and P-type respectively on different substrates, and then combined into p–n junction. Moreover, InSe/h-BN/Gr device can be switched freely between N-type resistance and p–n junction. The resistance value of InSe resistor and the photoelectric properties of the p–n junction are also sensitively modulated by laser. Under dark conditions, the rectification ratio of p–n junction can be as high as 107. After laser modulation, the device has a response up to 1.154 × 104 A W−1, a detection rate up to 5.238 × 1012 Jones, an external quantum efficiency of 5.435 × 106%, and a noise equivalent power as low as 1.262 × 10−16 W/Hz1/2. It lays a foundation for the development of high sensitivity and fast response rate tunable photoelectric p–n junction transistor.

Novel Self-Aligned Nitride One Time Programming with 2-bit/Cell Based on Pure 90-nm Complementary Metal–Oxide–Semiconductor Logic Technology

A novel 2-bit/cell one time programming (OTP) cell with a nitride-based storage node was developed for programmable logic applications. The fully-logic-compatible cell was successfully demonstrated using 90-nm complementary metal–oxide–semiconductor (CMOS) technology with a cell size of 0.358 µm2. This cell adopting source-side injection (SSI) programming scheme has a very large on/off window and superior writing efficiency. The self-aligned nitride storage node exhibits excellent data retention even at a logic gate oxide thickness of less than 2 nm. This new cell supports a promising solution for logic non-volatile memory (NVM) beyond the 90-nm node.

A New Antifuse Cell With Programmable Contact for Advance CMOS Logic Circuits

A new CMOS-process-compatible programmable contact antifuse (PCAF) cell is presented in this letter for advance programmable logic applications. This innovative PCAF cell adapts an oxide layer formed by the etched resist-protection oxide layer under a properly designed contact region, which results in a highly scalable one-time-programmable solution for advance logic circuits. A subcircuit model describing the - characteristics of the antifuse cell before and after program is developed to facilitate the future PCAF memory macro design.

A 0.26-$\mu\hbox{m}^{2}$ U-Shaped Nitride-Based Programming Cell on Pure 90-nm CMOS Technology

A novel one time programming (OTP) cell with a nitride-based storage has been developed for advanced programmable logic applications. This cell that is processed by pure logic process and decoupled with transistor gate oxide has a highly stable and extremely wide on/ off window. It exhibits a superior disturb immunity in program and read operations. In addition, a very small cell size (0.263 mum2 ) has been achieved using 90-nm pure CMOS logic process and is scalable in more advanced CMOS logic technologies by eliminating the constraint of transistor gate-oxide thickness. The all new OTP cell has a wide ON/OFF window and a superior writing efficiency by source-side injection programming mechanism. This novel OTP cell is a very promising programmable logic solution, with a fully CMOS-logic-compatible process below the 90-nm node.