Programmable Digital Filter Research Articles

A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers

This paper presents a long-term evolution (LTE) receiver (RX) front end with a digital filtering analog to digital converter (ADC) in the baseband to perform multi-band blocker cancellation. The digital filtering ADC has a digitally defined transfer function that is highly reconfigurable and insensitive to PVT variations. The dynamic range requirement of the blocker cancellation feedback digital to analog converter (DAC) is relaxed with a trivial uncalibrated first-order passive high-pass filter. The programmable digital filter provides 34.9-dB attenuation of transmitter leakage and variable attenuation of an additional blocker anywhere in the frequency range 17.5–107.5 MHz. A blocker detection algorithm for this RX is presented and takes approximately 26 $\mu \text{s}$ to converge. The RX front end operates at 1.8 GHz with a noise figure of 3.9 dB and IIP3 of −5 dBm, and consumes only 20.4–37.5 mW, the lowest among the state-of-the-art designs.

Improvement of analog-code converter

A problem of applying the ship of single-channel programmable digital filter QF1D512 from the company Quickfilter Technologies for processing of digital data stream o f analog-digital code converter during seismic signal registration has been considered.

Intelligent Digital Voltage Meter Design and Implement Based on AD7715

AD7715 is a high accuracy A/D converts chip made by American company Analog – Devices which involves a programmable gain amplifier, a programmable digital filter. It employs the Σ-Δ ADC technology to realize the 16-bits accurate measurement. The voltage meter uses 89C55 SCM as control, uses analog switch to conduct multi switch for measured voltage through signal conditioning, uses new 16-bit A/D convert to sample measured voltage being conditioned, uses 128 X 64 dot-matrix LCD as display screen to show the wave and Chinese words. This article mainly introduces the means of applying AD7715 chips to design accurate voltage meter.

Design of multi-standard NTSC/PAL video encoder

Abstract This paper presents the design of a multi-standard NTSC/PAL video encoder. The encoder converts International Telecommunication Union-Recommendation (ITU-R) BT.601 4:2:2, ITU-R BT.656 or RGB inputs from various video sources into National Television Standards Committee (NTSC) or phase-alternate line (PAL) TV signals in both S-video and composite video baseband signals (CVBS). The encoder adopts multiplier-free structures to reduce hardware complexity. The hardware bit width of programmable digital filters for luminance and chrominance signals, along with other operating blocks, are carefully determined to produce high-quality digital video signals of 1 least significant bit (LSB) error or less. The proposed encoder is experimentally demonstrated by using the Altera APEX20K600EBC652-3 device.

A real time programmable digital filter for biomedical signal enhancement incorporating a high-level design interface

A simple but highly integrated digital signal processing system is described for real time filtering of biomedical signals. It includes the necessary processing and communications hardware, the processing code itself and a high-level software interface that enables the user to design and download arbitrary finite impulse response filters to the run-time system. The filter coefficients are calculated using the frequency sampling method. Since the filters are realized using a finite impulse response, no phase distortion is introduced into the processed signals. A unique feature of the design is the manner in which the software and hardware components have been organized as an intelligent system, obviating on the part of the user a detailed knowledge of filter design theory or any abilities in processor architecture and assembly code programming.

Experimental CDMA data overlay of GSM network

A broadband 64 Kbit/s DS-CDMA overlay which operates on the same carrier frequency as a downlink GSM signal is proposed. Error free operation of both systems has been demonstrated over a 70 dB power range. A novel CDMA receiver architecture allowed programmable digital notch filters to be implemented directly at RF. It is shown that the overall network capacity is increased by a factor of 3.3 compared to the case of a single GSM carrier only, as detailed in a previous theoretical analysis. This represents the first experimental demonstration of a CDMA overlay of a GSM network.

Scalability of Programmable FIR Digital Filters

Previous designs of programmable FIR digital filters have demonstrated that the use of broadcast data and control can lead to a high performance-to-cost ratio. As the technology advances to the deep sub-micrometer regime, such an approach should be re-examined by taking the effect of interconnections into account. In this paper, we show that the contribution of interconnect delay to the cycle time is no longer negligible and will hamper the scalability of such broadcast designs. Further speed and density improvements through scaling can be secured by the fully pipelined design in which both data and control signals are restricted to local connections.

Development of an Active Attenuator for Pressure Pulsation in Liquid Piping Systems. 5th Report. Trial Construction of the Adaptive Control System and Fundamental Experiments.

A new technique for an active adaptive attenuator for wide-band pressure pulsation in liquid piping systems, which controls feed-forwardly the second source by the progressive wave component of fluid-borne vibration detected at the upstream of the pipeline and has the capability to change system parameters owing to a programmable digital filter, is presented together with computer simulation and experimental results. The adaptive feed-forward control structure is based on the so-called "Filtered-X LMS algorithm". It is established by the test in the small-sized model experimental pipeline that the pressure pulsation in a downstream pipe of the second source can be reduced to at least -20 dB for almost all harmonics of around 10 to 800 Hz, while maintaining the stability, even in the case where uncontrolled system parameters such as acoustic properties, dynamic characteristics of second source, etc., change with time. It is also shown that the computer simulation agrees well quantitatively with the experimental results and can be applied successfully to system design.

A programmable digital filter IC employing multiple processors on a single chip

A programmable general-purpose digital filter IC that employs multiple processing units on a single chip is described. The processors operate in parallel and communicate through on-chip dual-access storage register blocks. The processors are arranged as a ring with the locally shared register blocks between each adjacent pair of processors. It is shown that this ring of processors is capable of realizing a rich variety of filter structures operating at the maximum possible instruction execution rate. Fast real-time processing at video rates is obtained by using a fast hardware multiplier in each processor and by employing a design that permits each processor to simultaneously execute multiplication and addition operations in a single instruction cycle. An advantage of the design is the free passing of data between adjacent processors due to each register block's dual port. A ring of five such processors can be implemented in 2- mu m CMOS technology on a single 7.9 mm*9.2 mm chip operating at data rates up to 40 MHz. >

The implementation of digital echo cancellation in codecs

The architecture of a codec in which the echo cancellation is done in two stages, an analog hybrid to reduce the echo level at the input of the A/D converter and a programmable digital balance filter, is presented. The design problems connected with this architecture, such as the signal-to-noise performance of the A/D converter and the limiting effects of the variation of the analog components on the echo cancellation performance of the device and on the structure of the digital balance filters, are discussed. These results were used in the design of a single-power-supply CMOS device implemented in 1.5- mu m technology using Sigma Delta modulation techniques for A/D and D/A conversion. Its echo cancellation performance is sufficiently high that only one set of coefficients per national standard is necessary. >

Hardware implementation of programmable coefficients recursive digital filter

Hardware implementation of programmable coefficients recursive digital filter

Comparison of four hearing aid prescriptive procedures

A digital master hearing aid configured around a programmable digital filter was used to simulate hearing aids prescribed by four different procedures. The prescriptive procedures were modeled on those developed by Skinner, Byrne and Toonison, Lybarger, and Levitt et al. Real‐time simulation allowed for adaptive paired‐comparison testing to be used in evaluating the prescribed hearing aids. Data were obtained for three signal levels corresponding to input levels of 60 and 70 dB SPL and an output level corresponding to the subject's most comfortable loudness level. Speech discrimination scores were obtained for each simulated hearing aid at each signal level, as well as paired‐comparison judgments of relative intelligibility and overall quality. No single prescriptive procedure was found to be uniformly superior to the other procedures considered. Differences between procedures were largest at low signal levels and smallest at the subject's most comfortable level. [Research supported by NIHR.]

Self-adaptive broadband active sound control system

The principle and performance of a broadband active sound control system in an air-conditioning duct is described. The system presented, which is designed for industrial use, is self-adaptive thanks to a programmable digital filter. It is possible to obtain attenuations of between 20 and 25 dB over a frequency band from several tens of Hz up to the first transverse mode of the duct, the airflow rates being around 10 m/s. Its self-adaptive property means that fully equipped and preset sections can be built in the laboratory and can then be inserted on site in the same way as mufflers.

An approach to the realization of a programmable FIR digital filter

It is shown that by varying the tap coefficients of a generalized transversal filter structure consisting of a tapped cascade of identical FIR subfilters, it is possible to implement an FIR digital filter with adjustable magnitude response. By choosing a few different FIR structures as subfilters, an overall FIR filter with a wide variation in magnitude response can be realized. An implementation of the proposed programmable FIR filter using a commercially available DSP chip is illustrated along with experimental results.

Intelligibility of speech and its relationship to the speech spectrum—French and Steinberg revisited

Knowledge of the relationship between the speech spectrum and intelligibility of speech is a key factor in being able to maximize intelligibility for the hearing‐impaired listener and for the normal listener under such adverse conditions as bandwidth attenuation or masking by noise. The present experiment was designed to allow the speech spectrum to pass, binaurally, to a normal listener, with an optimally flat response of the electroacoustic system. A real‐time programmable digital filter was then used to allow only certain bandwidths of the spectrum to be heard by the listener. The bandwidth locations were chosen to include the formants of the talker's voice. The experimental results were then compared to the classic results of French and Steinberg. It was observed that high‐pass and low‐pass filter tests, generally, agreed with French and Steinberg's observations; however, it was also found that bandpass filter tests do not agree since comparison to the older experimental results is inappropriate. From these new results, a revised analytical procedure for intelligibility versus the speech spectrum is being developed.

A bit‐sliced design for a programmable digital filter

Abstract A 14‐span programmable low‐pass FIR digital filter is implemented with a decimation structure. With the aid of bitsliced technique, the tedious data flow that results from sharing unified arithmetic circuits can be operated in real‐time mode, and the sampling rate is up to 102.4 KHz.

A Microprocessor System for the Discrete-Time Control Laboratory

The topics studied in discrete-time signal processing and control are particularly abstract and some aid to learning these concepts is needed. One possible type of aid is discussed which employs state-of-the-art hardware to implement a programmable digital filter which may be useful in discussing sampling, digital filtering or may be inserted as a discrete-time compensator into a continuous-time control loop. The device employs modern microprocessor hardware including ROM, RAM, interval timer, digital-to-analog, and analog-to-digital converters. Digital filters up to fourth order may be programmed as may the sampling interval to be employed. Several applications to the control of a typical continuous-time plant are given.

The TAP III beamforming system

The Three-Array Processor (TAP III) beamforming system incorporating both wide-band time-domain beamforming and narrow-band frequency-domain beamforming is described. This paper briefly develops the beamforming theory and shows how the fast Fourier transform (FFT) is applied to accomplish frequency-domain beamforming. The frequency-domain beamformer operates in the frequency domain to form beams and power spectrum data over narrow frequency bands of interest. A real-time digital filtering technique is used to extract the narrow bands of interest from the broad-band input signal. The frequency-domain beamformer accomplishes real-time digital filtering and beamforming by using a high-speed array processor to do the complex calculations and data handling required by the algorithm. The time-domain beamformer operates in parallel with the frequency-domain beamformer to form up to 16 broad-band beams in the time domain. A programmable all-pass digital filter is used to create the fine time delays required by the time-domain beamformer.

Speed-optimised microprocessor implementation of a digital filter

A practical, efficient scheme is described for the implementation of a real-time programmable digital filter using a microprocessor. The use of distributed arithmetic is known to be able to provide increased speeds by avoiding time-consuming multiplications. To achieve maximum speeds, the working program in a microprocessor implementation should, as far as possible, contain only those instructions which perform the arithmetic functions. High component efficiency is also achieved if the inherent control capabilities of the microprocessor are fully utilised, in particular where support hardware elements are used. Simple techniques are proposed for meeting the above objectives, which are inexpensive to implement and are readily adaptable for most standard microprocessors. The low cost and enhanced speed of implementation makes it attractive as an economical alternative to hard-wired digital filters for working frequencies in the audio and telephony range of frequencies and as a building block for cascade realisation of larger length filters, particularly of the FIR type. Some results of an experimental model using the commercial standard 8080A micropressor are given and comparisons with implementations for other micropressors are made.

Use of a programmable filter for inverse filtering

A real-time deconvolution or inverse filter, operating at signal frequencies up to 5 MHz, is reported. The programmable digital filter is controlled by a computer which calculates the Wiener-filter solution using f.f.t. techniques. Deconvolved signals can be clearly discriminated after passing through a distorting medium.