Processors Of Different Speeds Research Articles

Computing the Price of Anarchy in Processor Load Balancing Game with Linear Delays

This paper considers a generalization of the processor load balancing game also known as KP-model. A linear delay of a processor may depend on not only its load but on loads of other processors. Players choose processors of different speeds to run their jobs striving to minimize job's delay, i.e., the job completion time on a chosen processor. The social cost is the maximum delay over all processors. We propose a computing algorithm of the exact PoA value which can be applied to estimate the POA visually if its exact analytical expression is not obtained yet or it is rather complicated to figure out its formula.

Parallel simulation of three-dimensional complex flows: Application to two-phase compressible flows and turbulent wakes

In this paper, we present parallel simulations of three-dimensional complex flows obtained on an ORIGIN 3800 computer and on homogeneous and heterogeneous (processors of different speeds and RAM) computational grids. The solver under consideration, which is representative of modern numerics used in industrial computational fluid dynamics (CFD) software, is based on a mixed element-volume method on unstructured tedrahedrisations. The parallelisation strategy combines mesh partitioning techniques, a message-passing programming model and an additive Schwarz algorithm. The parallelisation performances are analysed on a two-phase compressible flow and a turbulent flow past a square cylinder.

Online Scheduling of Parallel Programs on Heterogeneous Systems with Applications to Cilk

We study the problem of executing parallel programs, in particular Cilk programs, on a collection of processors of different speeds. We consider a model in which each processor maintains an estimate of its own speed, where communication between processors has a cost, and where all scheduling must be online. This problem has been considered previously in the fields of asynchronous parallel computing and scheduling theory. Our model is a bridge between the assumptions in these fields. We provide a new more accurate analysis of an old scheduling algorithm called the maximum utilization scheduler . Based on this analysis, we generalize this scheduling policy and define the high utilization scheduler . We next focus on the Cilk platform and introduce a new algorithm for scheduling Cilk multithreaded parallel programs on heterogeneous processors. This scheduler is inspired by the high utilization scheduler and is modified to fit in a Cilk context. A crucial aspect of our algorithm is that it keeps the original spirit of the Cilk scheduler. In fact, when our new algorithm runs on homogeneous processors, it exactly mimics the dynamics of the original Cilk scheduler.

ALGORITHMIC ISSUES ON HETEROGENEOUS COMPUTING PLATFORMS

This paper discusses algorithmic issues when computing with a heterogeneous network of work-stations (the typical poor man's parallel computer). Dealing with processors of different speeds requires to use more involved strategies than block-cyclic data distributions. Dynamic data distribution is a first possibility but may prove impractical and not scalable due to communication and control overhead. Static data distributions tuned to balance execution times constitute another possibility but may prove ineffcient due to variations in the processor speeds (e.g. because of different workloads during the computation). We introduce a static distribution strategy that can be refined on the fly, and we show that it is well-suited to parallelizing scientific computing applications such as finite-difference stencils or LU decomposition.

Scheduling complete intrees on two uniform processors with communication delays

We present an optimal algorithm for scheduling a complete k-ary tree on two uniform processors of different speeds in order to minimize schedule length. We consider the basic case of unit standard execution times and unit communication times.

ANALYSIS OF TRAINING SET PARALLELISM FOR BACKPROPAGATION NEURAL NETWORKS

Training set parallelism and network based parallelism are two popular paradigms for parallelizing a feedforward (artificial) neural network. Training set parallelism is particularly suited to feedforward neural networks with backpropagation learning where the size of the training set is large in relation to the size of the network. This paper analyzes training set parallelism for feedforward neural networks when implemented on a transputer array configured in a pipelined ring topology. Theoretical expressions for the time per epoch (iteration) and optimal size of a processor network are derived when the training set is equally distributed among the processing nodes. These show that the speed up is a function of the number of patterns per processor, communication overhead per epoch and the total number of processors in the topology. Further analysis of how to optimally distribute the training set on a given processor network when the number of patterns in the training set is not an integer multiple of the number of processors, is also carried out. It is shown that optimal allocation of patterns in such cases is a mixed integer programming problem. Using this analysis it is found that equal distribution of training patterns among the processors is not the optimal way to allocate the patterns even when the training set is an integer multiple of the number of processors. Extension of the analysis to processor networks comprising processors of different speeds is also carried out. Experimental results from a T805 transputer array are presented to verify all the theoretical results.

STATIC HEURISTIC PROCESSOR ASSIGNMENT IN HETEROGENEOUS MULTIPROCESSORS

It has been already demonstrated that cost-effective multiprocessor designs may be obtained by combining in the same architecture processors of different speeds (heterogeneous architecture) so that the serial and critical portions of the application may benefit from a fast single processor. In such an environment, the problem of assigning tasks to processors becomes a very important one. This papers presents a systematic way to build static heuristic scheduling algorithms. Using this strategy, several algorithms are proposed and their performance are compared through simulation. One of the proposed algorithms is shown to achieve substantial performance gains as the degree of heterogeneity of the architecture increases.

Efficient scheduling of tasks without full use of processor resources

The nonpreemptive scheduling of a partially ordered set of tasks on a machine with m processors of different speeds is studied. Polynomial time algorithms are presented which benefit from selective non-use of slow processors. The performance of these heuristics is asymptotic to √ m times worse than optimal, whereas list schedules are unboundedly worse than optimal for any fixed value of m. The techniques of analyzing these schedules are used to obtain a bound on a large class of preemptive schedules.

A Level Algorithm for Preemptive Scheduling

Muntz and Coffman give a level algorithm that constructs optimal preemptive schedules on identical processors when the task system is a tree or when there are only two processors available. Their algorithm is adapted here to handle processors of different speeds. The new algorithm is optimal for independent tasks on any number of processors and for arbitrary task systems on two processors, but not on three or more processors, even for trees. By taking the algorithm as a heuristic onmprocessors and using the ratio of the lengths of the constructed and optimal schedules as a measure, an upper bound on its performance is derived in terms of the speeds of the processors. It is further shown that 1.23√mis an upper bound over all possible processor speeds and that the 1.23√mbound can be improved at most by a constant factor, by giving an example of a system for which the bound 0.35√mcan be approached asymptotically.

Analysis of a level algorithm for preemptive scheduling

Muntz and Coffman give a level algorithm that constructs optimal preemptive schedules on identical processors when the task system is a tree or when there are only two processors. A variation of their algorithm is adapted for processors of different speeds. The algorithm is shown to be optimal on two processors for arbitrary task systems, but not on three or more processors even for trees. Taking the algorithm as a heuristic on m processors and using the ratio of the lengths of the constructed and optimal schedules as a measure, we show that, on identical processors, its performance is bounded by 2 - 2/m. Moreover 2 - 2/m is a best bound in that there exist task systems for which this ratio is approached arbitrarily closely. On processors of different speeds, we derive an upper bound of its performance in terms of the speeds of the given processor system and show that @@@@1.5m is an upper bound over all processor systems. We also give an example of a system for which the bound @@@@m/2 @@@@2 can be approached asymptotically, thus establishing that the @@@@1.5m bound can at most be improved by a constant factor.