Processor Topology Research Articles

Prelude to Simulations of Loop Quantum Gravity on Adiabatic Quantum Computers

The article addresses the possibility of implementing spin network states, used in the loop quantum gravity approach to Planck scale physics on an adiabatic quantum computer. The discussion focuses on applying currently available technologies and analyzes a concrete example of a D-Wave machine. It is introduced a class of simple spin network states which can be implemented on the Chimera graph architecture of the D-Wave quantum processor. However, extension beyond the currently available quantum processor topologies is required to simulate more sophisticated spin network states. This may inspire new generations of adiabatic quantum computers. A possibility of simulating loop quantum gravity is discussed, and a method of solving a graph non-changing scalar (Hamiltonian) constraint with the use of adiabatic quantum computations is proposed. The presented results establish a basis for the future simulations of Planck scale physics, specifically quantum cosmological configurations, on quantum annealers.

An OpenGL Compliant Hardware Implementation of a Graphic Processing Unit Using Field Programmable Gate Array–System on Chip Technology

FPGA-SoC technology provides a heterogeneous platform for advanced, high-performance systems. The System on Chip (SoC) architecture combines traditional single and multiple core processor topologies with flexible FPGA fabric. Dynamic reconfiguration allows the hardware accelerators to be changed at run-time. This article presents a novel OpenGL compliant GPU design implemented on an FPGA. The design uses an FPGA-SoC environment allowing the embedded processor to offload graphics operation onto a more suitable architecture. To the authors’ knowledge, this is a first. The graphics processor consists of GLSL compliant shaders, an efficient Barycentric Rasterizer, and a draw mode manager. Performance analysis shows the throughput of the shaders to be hundreds of millions of vertices per second. The design uses both pipelining and resource reuse to optimise throughput and resource use, allowing implementation on a low-cost, FPGA device. Pixel processing rates from this implementation are almost 80% higher than other FPGA implementations. Power consumption compared with comparative embedded devices shows the FPGA consuming as little as 2% of the power of a Mali device, and an up to 11.9-fold increase in efficiency compared to an Nvidia RTX 2060 - Turing architecture device.

CPL library — A minimal framework for coupled particle and continuum simulation

We present an open-source library for coupling particle codes, such as molecular dynamics (MD) or the discrete element method (DEM), and grid based computational fluid dynamics (CFD). The application is focused on domain decomposition coupling, where a particle and continuum software model different parts of a single simulation domain with information exchange. This focus allows a simple library to be developed, with core mapping and communication handled by just four functions. Emphasis is on scaling on supercomputers, a tested cross-language library, deployment with containers and well-documented simple examples. Building on this core, a template is provided to facilitate the user development of common features for coupling, such as averaging routines and functions to apply constraint forces. The interface code for LAMMPS and OpenFOAM is provided to both include molecular detail in a continuum solver and model fluids flowing through a granular system. Two novel development features are highlighted which will be useful in the development of the next generation of multi-scale software: (i) The division of coupled code into a smaller blocks with testing over a range of processor topologies. (ii) The use of coupled mocking to facilitate coverage of various parts of the code and allow rapid prototyping. These two features aim to help users develop coupled models in a test-driven manner and focus on the physics of the problem instead of just software development. All presented code is open-source with detailed documentation on the dedicated website (cpl-library.org) permitting useful aspects to be evaluated and adopted in other projects. Program summaryProgram Title:CPLLIBRARYProgram Files doi:http://dx.doi.org/10.17632/9dh8w97d2x.1Licensing provisions: GPLv3Programming languages: Fortran/C/C++/PythonExternal routines/libraries: Message Passing Interface (MPI)Nature of problem: Coupling of particle and continuum software to enable simulations not possible with either code alone. In particular, handling communication and interaction of computational fluid dynamics (CFD) software with either molecular dynamics (MD) or discrete element method (DEM) solvers on high performance computing (HPC) platforms.Solution method: A shared library with a minimal set of functions to enable coupling, together with an entire infrastructure to facilitate development of validated coupled software. This includes a minimal Python interface to encourage mock testing, libraries to help develop coupled tools along with pre-coupled examples including OpenFOAM, LAMMPS, Flowmol (Smith, 2014) and interactive plotting using wxPython and matplotlib.Unusual features: Minimal interface with simple setup. A CPL_Mocks framework to facilitate debugging and test driven development. Communication established between independent executables using MPI_Open_Port, reducing required changes to core source code. Coupled codes track the git repository with validation through continuous integration testing and deployment on DockerHub. All communication based on MPI_Cart and MPI_Graph so optimisation is possible through MPI implementation on supercomputers.

A QDWH-based SVD Software Framework on Distributed-memory Manycore Systems

This article presents a high-performance software framework for computing a dense SVD on distributed-memory manycore systems. Originally introduced by Nakatsukasa et al. (2010) and Nakatsukasa and Higham (2013), the SVD solver relies on the polar decomposition using the QR Dynamically Weighted Halley algorithm (QDWH). Although the QDWH-based SVD algorithm performs a significant amount of extra floating-point operations compared to the traditional SVD with the one-stage bidiagonal reduction, the inherent high level of concurrency associated with Level 3 BLAS compute-bound kernels ultimately compensates for the arithmetic complexity overhead. Using the ScaLAPACK two-dimensional block cyclic data distribution with a rectangular processor topology, the resulting QDWH-SVD further reduces excessive communications during the panel factorization, while increasing the degree of parallelism during the update of the trailing submatrix, as opposed to relying on the default square processor grid. After detailing the algorithmic complexity and the memory footprint of the algorithm, we conduct a thorough performance analysis and study the impact of the grid topology on the performance by looking at the communication and computation profiling trade-offs. We report performance results against state-of-the-art existing QDWH software implementations (e.g., Elemental) and their SVD extensions on large-scale distributed-memory manycore systems based on commodity Intel x86 Haswell processors and Knights Landing (KNL) architecture. The QDWH-SVD framework achieves up to 3/8-fold speedups on the Haswell/KNL-based platforms, respectively, against ScaLAPACK PDGESVD and turns out to be a competitive alternative for well- and ill-conditioned matrices. We finally come up herein with a performance model based on these empirical results. Our QDWH-based polar decomposition and its SVD extension are freely available at https://github.com/ecrc/qdwh.git and https://github.com/ecrc/ksvd.git, respectively, and have been integrated into the Cray Scientific numerical library LibSci v17.11.1.

An embedded sectioning scheme for multiprocessor topology-aware mapping of irregular applications

We consider the problem of mapping irregular applications to multiprocessor architectures whose interconnect topologies affect the latencies of data movement across processor nodes. The starting point for solutions to this problem concerns suitable weighted graph representations of an irregular application and a processor topology. Prior results for this problem have demonstrated that graph partitioning approaches can provide high-quality solutions. Additionally, when coordinate information is available for the weighted graph of the application, the geometric mapping schemes can also provide high-quality solutions. We develop and present a scheme that we call ‘embedded sectioning’ that directly computes a locality enhancing embedding of the weighted graph representation which is then mapped to the processor topology using recursive coordinate bisection. Our scheme is specifically directed at gaining high-quality mappings for highly irregular applications where the amount of communication can vary greatly. We evaluate the quality of mappings produced by embedded sectioning for mesh-based processor topologies using well-accepted measures including congestion, dilation and their product, referred to as the communication volume. For a test suite of unit-weight graphs mapped to a 32 × 32 mesh of processors, our method improves congestion by 26%, dilation by 52% and communication volume by 64% relative to the best values of these measures from nine other schemes. Additionally, we observe that these improvements increase with an increase in the skewness of communication in applications. For a test suite with a skewness of two the corresponding improvements for congestion, dilation and communication volume are 72%, 52% and 87%, respectively.

Enhanced Differential Power Processor for PV Systems: Resonant Switched-Capacitor Gyrator Converter With Local MPPT

This paper introduces an enhanced differential power processor topology and principle of operation for photovoltaic (PV) systems that is based on switched-capacitor technology, featuring local maximum power point tracking (MPPT) capability, zero current switching, high efficiency over wide-operation range, and reduced size. The new converter operates as a voltage-dependent current-source and is regulated by dead-time or frequency control. Local MPPT on the individual PV elements is realized and the operation is demonstrated by simulation and experiments. Differential power processing operation is verified using 150-W prototypes, demonstrating ultimate improvement in the power harvesting capability of above 90% and up to 99% out of the available power in the string, under different insolation levels.

MLMIN: A multicore processor and parallel computer network topology for multicast

In future, multicore processors with hundreds of cores will collaborate on a single chip. Then, more advanced network-on-chip (NoC) topologies will be needed than today's shared busses for dual core processors. Multistage interconnection networks, which are already used in parallel computers, seem to be a promising alternative. In this paper, a new network topology is introduced that particularly applies to multicast traffic in multicore systems and parallel computers. Those multilayer multistage interconnection networks are described by defining the main parameters of such a topology. Performance and costs of the new architecture are determined and compared to other network topologies. Network traffic consisting of constant size packets and of varying size packets is investigated. It is shown that all kinds of multicast traffic particularly benefit from the new topology.

A parallel SML compiler based on algorithmic skeletons

Algorithmic skeletons are abstractions from common patterns of parallel activity which offer a high degree of reusability for developers of parallel algorithms. Their close association with higher order functions (HOFs) makes functional languages, with their strong transformational properties, excellent vehicles for skeleton-based parallel program development. However, using HOFs in this way raises substantial problems of identification of useful HOFs within a given application and of resource allocation on target architectures. We present the design and implementation of a parallelising compiler for Standard ML which exploits parallelism in the familiar $map$ and $fold$ HOFs through skeletons for processor farms and processor trees, respectively. The compiler extracts parallelism automatically and is target architecture independant. HOF execution within a functional language can be nested in the sense that one HOF may be passed and evaluated during the execution of another HOF. We are able to exploit this by nesting our parallel skeletons in a processor topology which matches the structure of the Standard ML source. However, where HOF arguments result from partially applied functions, free variable bindings must be identified and communicated through the corresponding skeleton hierarchy to where those arguments are actually applied. We describe the analysis leading from input Standard ML through HOF instantiation and backend compilation to an executable parallel program. We also present an overview of the runtime system and the execution model. Finally, we give parallel performance figures for several example programs, of varying computational loads, on the Linux-based Beowulf, IBM SP/2, Fujitsu AP3000 and Sun StarCat 15000 MIMD parallel machines. These demonstrate good cross-platform consistency of parallel code behaviour.

Photonic bandpass filters with high skirt selectivity and stopband attenuation

A new photonic signal processor topology that simultaneously achieves both a high-Q and a high skirt selectivity and stopband attenuation filter response is presented. It is based on a novel dual-cavity bandpass optical structure in which two pairs of active fiber Bragg grating cavities are used with an optical gain offset to control the poles and stopband attenuation characteristics of the filter. This concept enables a large improvement in the filter stopband attenuation, rejection bandwidth, and skirt selectivity to be realized. Measured results demonstrate both a narrow bandpass bandwidth of 0.4% of center frequency and a skirt selectivity factor of 16.6 for 40 dB rejection, which corresponds to a 6.5-fold improvement in comparison to conventional single cavity high-Q structures. To our knowledge, this is the best skirt selectivity reported for a photonic bandpass filter to date. The new photonic filter structure has been experimentally verified and excellent agreement between measured and predicted responses is shown.

A Scalable Strategy for the Parallelization of Multiphysics Unstructured Mesh-Iterative Codes on Distributed-Memory Systems

Realizing scalable performance on high performance computing systems is not straightforward for single-phenomenon codes (such as computational fluid dynamics [CFD]). This task is magnified considerably when the target software involves the interactions of a range of phenomena that have distinctive solution procedures involving different discretization methods. The problems of addressing the key issues of retaining data integrity and the ordering of the calculation procedures are significant. A strategy for parallelizing this multiphysics family of codes is described for software exploiting finite-volume discretization methods on unstructured meshes using iterative solution procedures. A mesh partitioning-based SPMD approach is used. However, since different variables use distinct discretization schemes, this means that distinct partitions are required; techniques for addressing this issue are described using the mesh-partitioning tool, JOSTLE. In this contribution, the strategy is tested for a variety of test cases under a wide range of conditions (e.g., problem size, number of processors, asynchronous/synchronous communications, etc.) using a variety of strategies for mapping the mesh partition onto the processor topology.

Simulated annealing task to processor mapping for domain decomposition methods on distributed parallel computers

The parallel solution of large sets of equations derived from finite element or finite difference methods often involves the use of domain decomposition methods. This paper is concerned with the related problem of mapping subdomain partitioning to a processor topology in such a way that the communication overheads during solution are minimized. In this manner, processors far away from each other in the processor network are not required to communicate directly. This is achieved by solving an optimization problem using the simulated annealing method. The techniques described here can be applied more generally to distribute tasks (as opposed to subdomains) to processors. Copyright © 1999 John Wiley & Sons, Ltd.

High-Q optical microwave filter

A new photonic signal processor topology is presented, which achieves high-Q value microwave bandpass filtering. It significantly increases the Q by means of a small free spectral range passive filter, while still operating the active stage with a large gain margin. The filter response demonstrates very high resolution microwave signal filtering with a measured Q value of 983.

Object Location by Parallel Pose Clustering

This paper describes the location of 3D objects in either depth or intensity data using parallel pose clustering. A leader-based partitional algorithm is used that allows the number of clusters to be selected on the basis of the input data, which is important because the number of pose clusters cannot usually be determined in advance. In comparison with previous work, no assumptions are made about the number or distribution of data patterns, or that the processor topology should be matched to this distribution. After overcoming a parallel bottleneck, we show that our approach exhibits superlinear speedup, since the overall computation is reduced in the parallel system. Isolated pose estimates may be eliminated from the cluster space after an initial stage, which may be done with low probability of missing a true cluster. The algorithm has been tested using real and synthetic data on a transputer-based MIMD architecture.

Optimal task assignment in heterogeneous distributed computing systems

A distributed system comprising networked heterogeneous processors requires efficient task-to-processor assignment to achieve fast turnaround time. Although reasonable heuristics exist to address optimal processor assignment for small problems, larger problems require better algorithms. The authors describe two new algorithms based on the A* technique which are considerably faster, are more memory-efficient, and give optimal solutions. The first is a sequential algorithm that reduces the search space. The second proposes to lower time complexity, by running the assignment algorithm in parallel, and achieves significant speedup. The authors test their results on a library of task graphs and processor topologies.

Parallel image understanding algorithms on MIMD multicomputers

The heterogeneous nature of data types and computational structures involved in Computer Vision algorithms make the design and implementation of massively parallel image processing systems a not yet fully solved problem. It is common belief that in the next future MIMD architectures with their high degree of flexibility will play a very important role in this research area, by using a limited number of identical but powerful processing elements. The aim of this paper is to show how a selected list of algorithms in which a unique Image Understanding process can be decomposed could map onto a distributed-memory MIMD architecture. The operative modalities we adopt are the SPMD modality for the low level processing and the MIMD modality for the intermediate and high levels of processing. Either efficient parallel formulations of the algorithms with respect to the interconnection topology of processors and their optimized implementations on a target transputer-based architecture are reported.

Formula omitted]-graphs: Scalable topology and design of balanced divide-and-conquer algorithms

A parallel implementation of binary, balanced divide-and-conquer is derived systematically from its functional specification. The implementation makes use of a new processor topology, called N -graph, and has the following properties: there are not more than 4 links per processor, the processor network is of an arbitrary fixed size, the load is balanced and all communications are local. A parallel mergesort algorithm is used to illustrate the derivation process and the parallel target program with message passing. Experiments on a 64-node transputer network are presented.

Load balancing by redundant decomposition and mapping

In this paper a new methodology for load balancing parallel processes on parallel systems is proposed. The problem of load balancing is considered to be an NP-hard optimization task. Taking static parallel finite element applications as a case study, the benefits and losses that follow from applying the methodology are studied. It is found that the proposed methodology can be especially useful for load balancing in asymmetric processor topologies, and therefore is of importance for work load balancing in workstation clusters.

From transformations to methodology in parallel program development: A case study

The Bird-Meertens formalism (BMF) of higher-order functions over lists is a mathematical framework supporting formal derivation of algorithms from functional specifications. This paper reports results of a case study on the systematic use of BMF in the process of parallel program development. We develop a parallel program for polynomial multiplication, starting with a straight-forward mathematical specification and arriving at the target processor topology together with a program for each processor of it. The development process is based on formal transformations; design decisions concerning data partitioning, processor interconnections, etc. are governed by formal type analysis and performance estimation rather than made ad hoc. The parallel target implementation is parameterized for an arbitrary number of processors; for the particular number, the target program is both time and cost-optimal. We compare our results with systolic solutions to polynomial multiplication.

Efficient nonblocking switching networks for interprocessor communications in multiprocessor systems

The performance of a multiprocessor system depends heavily on its ability to provide conflict free paths among its processors. In this paper, we explore the possibility of using a nonblocking network with O(N log N) edges (crosspoints) to interconnect the processors of an N processor system, We combine Bassalygo and Pinsker's implicit design of strictly nonblocking networks with an explicit construction of expanders to obtain a strictly nonblocking network with -765.18N+352.8N log N edges and 2+log(N/5) depth. We present an efficient parallel algorithm for routing connection requests on this network and implement it on three parallel processor topologies. The implementation on a parallel processor whose processing elements are interconnected as in the Bassalygo-Pinsker network requires O(N log N) processing elements, O(N log N) interprocessor links and it takes O(log N) steps to route any single connection request where each step involves a small number (/spl ap/72) of bit-level operations. A contracted or folded version of the same implementation reduces the processing element count to O(N) without increasing the link count or the routing time. Finally, we establish that the same algorithm takes O(log/sup 3/ N) steps on a perfect shuffle processor with O(N) processing elements. These results improve the crosspoint, depth and routing time complexities of the previously reported strictly nonblocking networks. >

Contention-free 2D-mesh cluster allocation in hypercubes

Traditionally, each job in a hypercube multiprocessor is allocated with a subcube so that communication interference among jobs may be avoided. Although the hypercube is a powerful processor topology, the 2D mesh is a more popular application topology. This paper presents a 2D-mesh cluster allocation strategy for hypercubes. The proposed auxiliary free list processor allocation strategy can efficiently allocate 2D-mesh dusters without size constraints, can reduce average job turnaround time compared with that based on subcube allocation strategies, and can guarantee no communication interference among allocated clusters when the underlying hypercube implements deadlock-free E-cube routing. The proposed auxiliary free list strategy can be easily implemented on hypercube multicomputers to increase processor utilization.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>