Processor Network Topologies Research Articles

Parallel transient dynamic non-linear analysis of reinforced concrete plates

This article describes how parallel processing may improve the computational efficiency of the transient dynamic non-linear analysis of reinforced concrete plates subjected to blast or seismic loading. A parallel scheme for the time marching procedure is presented using the explicit Newmark’s algorithm. The finite element formulation with the material modelling (of a strain-rate sensitive hardening–softening, elasto–viscoplastic model accounting for cracking and crushing) is described. The complexity of the material laws and their modelling, induced by the extreme loading conditions, requires vast computational effort per time step. It will be shown that very high computational efficiency may be obtained by decomposing the finite element mesh into a number of sub-domains for distributed analysis on multiple processors. This high efficiency is achieved using distributed memory MIMD architectures (including transputer networks), where the routing of the messages represents significant overhead in terms of inter-processor communication because of limitations resulting from the processor network topology. Through examples it will be demonstrated how this efficiency depends on the problem size (i.e. the level of refinement of the problem idealisation), the number of sub-domains and the status of the analysis with regards to the states of the material.

Parallel computation of configuration space

SUMMARYMany motion planning methods use Configuration Space to represent a robot manipulator's range of motion and the obstacles which exist in its environment. The Cartesian to Configuration Space mapping is computationally intensive and this paper describes how the execution time can be decreased by using parallel processing. The natural tree structure of the algorithm is exploited to partition the computation into parallel tasks. An implementation programmed in the occam2 parallel computer language running on a network of INMOS transputers is described. The benefits of dynamically scheduling the tasks onto the processors are explained and verified by means of measured execution times on various processor network topologies. It is concluded that excellent speed-up and efficiency can be achieved provided that proper account is taken of the variable task lengths in the computation.

Real-time simulation of videophone image coding algorithms on reconfigurable multicomputers

The simulation at bit stream level of motion video image coding algorithms provides an effective means of algorithm development and evaluation. This paper describes the problems encountered in using a large reconfigurable transputer-based multicomputer to simulate, in real-time, realistically complex videophone image coding algorithms. A primary aim was to enable the output of all stages of the algorithm to be displayed graphically. This led to further communications bandwidth requirements which demanded that unusual processor network topologies were experimented with. For the large numbers of transputers used, it was found that irregular topologies provide better performance than previously popular regular ones.