Processor Idle Time Research Articles

A Comprehensive Analysis of Parallel Genetic Algorithms

The paper introduces an optimal approach for optimizing the idle time of processors through the utilization of parallel genetic algorithms. By harnessing the power of parallelism, we propose a method that effectively minimizes idle periods in processor operations. Our approach, outlined in detail within this paper, demonstrates significant improvements in resource utilization and efficiency. Through rigorous experimentation and analysis, we illustrate the efficacy of our parallel genetic algorithm in optimizing processor idle time. The findings presented herein offer promising insights into enhancing computational resource utilization, particularly in multi-processor systems. This research contributes to the ongoing efforts in maximizing computational efficiency and lays a foundation for further advancements in parallel optimization techniques. Keywords: Optimization; Metaheuristic; Parallel Genetic algorithm; Crossover; Mutation; Selection; Evolution;

Multi-Objective Genetic Algorithm-Based Technique for Achieving Low-Power VLSI Circuit Partition

Minimizing the power consumption of electronic systems is one of the most critical concerns in the design of integrated circuits for very large-scale integration (VLSI). Despite the reality that VLSI design is known for its compact size, low power, low price, excellent dependability, and high functionality, the design stage remains difficult to improve in terms of time and power. Several optimization algorithms have been designed to tackle the present issues in VLSI design. This study discusses a bi-objective optimization technique for circuit partitioning based on a genetic algorithm. The motivation for the proposed research is derived from the basic concept that, if some portions of a circuit's system are deactivated during the processor's idle time, the circuit's power consumption is automatically reduced. To reduce the overall system's power consumption, maximization of sleep time and minimization of net cuts are required. To achieve these, an effective fitness function has been constructed in such a way that the balance criteria are also maintained. The approach has been tested on a set of net lists from the ISPD'98 benchmark suite, each containing 10 to 30 nodes. The experimental results are compared with two existing methods that clearly indicate the acceptability of the suggested method. The suggested strategy achieves an average reduction of 24.69% and 31.46% for net cut, whereas average extensions of 15.20% and 12.31% are observed in sleep time when compared with two existing methods. The proposed method also achieves an average power efficiency of 14.98% and 12.09% with respect to these two state-of-the-art methods.

Appointment scheduling with a quantile objective

Appointment scheduling has many applications (e.g., surgery scheduling, airport gate scheduling, container vessel dockings and radiation therapy bookings) and it has a direct and significant operational and economic impact. For example, in healthcare, surgical departments are one of the main drivers of hospital costs and revenue, and appointment scheduling is used to book surgeries. Effective scheduling not only enables patients’ timely access to care but also enables more efficient operations. This becomes especially important as healthcare costs and demand are on the rise in many countries. We study appointment scheduling where there are jobs (e.g., patients, container vessels, airplanes) with random processing durations, an expensive processor (e.g., a doctor, dock crane, airport gate) and significant costs for processor idle time, processor overtime, and job waiting. The goal is to determine an appointment schedule that minimizes a measure of total costs as the objective. The appointment scheduling problem has been well studied in the literature with the expected cost objective. Almost all papers in the literature on appointment scheduling use the expected cost criterion, which may not be suitable when risk measures and/or service levels are considered. In this paper, we study this problem with a new objective: minimization of any quantile of the cost distribution, e.g., median, 90th percentile. We obtain theoretical results for some special cases and develop an algorithm for the general case. Our algorithm does not require a specific distribution assumption and can work directly with data samples. We present numerical examples with real data on surgeries. Our results show that allocated schedules based on the quantile objective with identical jobs are different than the ones generated by the expected cost objective and they do not show the well-known dome-shaped pattern but a semi-dome-shaped pattern which first increases (like the dome-shaped pattern) but then its decrease is not monotone (unlike the dome-shaped pattern). To the best of our knowledge, this is the first paper on appointment scheduling problem with the objective of the quantile function minimization.

Large-scale stochastic topology optimization using adaptive mesh refinement and coarsening through a two-level parallelization scheme

Topology optimization under uncertainty of large-scale continuum structures is a computational challenge due to the combination of large finite element models and uncertainty propagation methods. The former aims to address the ever-increasing complexity of more and more realistic models, whereas the latter is required to estimate the statistical metrics of the formulation. In this work, the computational burden of the problem is addressed using a sparse grid stochastic collocation method, to calculate the statistical metrics of the topology optimization under uncertainty formulation, and a parallel adaptive mesh refinement method, to efficiently solve each of the stochastic collocation nodes. A two-level parallel processing scheme (TOUU-PS2) is proposed to profit from parallel computation on distributed memory systems: the stochastic nodes are distributed through the distributed memory system, and the efficient computation of each stochastic node is performed partitioning the problem using a domain decomposition strategy and solving each subdomain using an adaptive mesh refinement method. A dynamic load-balancing strategy is used to balance the workload between subdomains, and thus increasing the parallel performance by reducing processor idle time. The topology optimization problem is addressed using the topological derivative concept in combination with a level-set method. The performance and scalability of the proposed methodology are evaluated using several numerical benchmarks and real-world applications, showing good performance and scalability up to thousands of processors.

On the partial synchronization of iterative methods

The rapidly growing field of parallel computing systems promotes the study of parallel algorithms, with the Monte Carlo method and asynchronous iterations being among the most valuable types. These algorithms have a number of advantages. There is no need for a global time in a parallel system (no need for synchronization), and all computational resources are efficiently loaded (the minimum processor idle time). The method of partial synchronization of iterations for systems of equations was proposed by the authors earlier. In this article, this method is generalized to include the case of nonlinear equations of the form x = F(x), where x is an unknown column vector of length n, and F is an operator from ℝ n into ℝ n . We consider operators that do not satisfy conditions that are sufficient for the convergence of asynchronous iterations, with simple iterations still converging. In this case, one can specify such an incidence of the operator and such properties of the parallel system that asynchronous iterations fail to converge. Partial synchronization is one of the effective ways to solve this problem. An algorithm is proposed that guarantees the convergence of asynchronous iterations and the Monte Carlo method for the above class of operators. The rate of convergence of the algorithm is estimated. The results can prove useful for solving high-dimensional problems on multiprocessor computational systems.

On partial synchronization of iterative methods

The rapidly growing field of parallel computing systems promotes the study of parallel algorithms, with the Monte Carlo method and asynchronous iterations being among the most valuable types. These algorithms have a number of advantages. There is no need for a global time in a parallel system (no need for synchronization), and all computational resources are efficiently loaded (the minimum processor idle time). The method of partial synchronization of iterations for systems of equations was proposed by the authors earlier. In this article, this method is generalized to include the case of nonlinear equations of the form x = F(x), where x is an unknown column vector of length n, and F is an operator from ℝn into ℝn. We consider operators that do not satisfy conditions that are sufficient for the convergence of asynchronous iterations, with simple iterations still converging. In this case, one can specify such an incidence of the operator and such properties of the parallel system that asynchronous iterations fail to converge. Partial synchronization is one of the effective ways to solve this problem. An algorithm is proposed that guarantees the convergence of asynchronous iterations and the Monte Carlo method for the above class of operators. The rate of convergence of the algorithm is estimated. The results can prove useful for solving high-dimensional problems on multiprocessor computational systems.

Revisiting Asynchronous Linear Solvers

Asynchronous methods for solving systems of linear equations have been researched since Chazan and Miranker's [1969] pioneering paper on chaotic relaxation. The underlying idea of asynchronous methods is to avoid processor idle time by allowing the processors to continue to make progress even if not all progress made by other processors has been communicated to them. Historically, the applicability of asynchronous methods for solving linear equations has been limited to certain restricted classes of matrices, such as diagonally dominant matrices. Furthermore, analysis of these methods focused on proving convergence in the limit. Comparison of the asynchronous convergence rate with its synchronous counterpart and its scaling with the number of processors have seldom been studied and are still not well understood. In this article, we propose a randomized shared-memory asynchronous method for general symmetric positive definite matrices. We rigorously analyze the convergence rate and prove that it is linear and is close to that of the method's synchronous counterpart if the processor count is not excessive relative to the size and sparsity of the matrix. We also present an algorithm for unsymmetric systems and overdetermined least-squares. Our work presents a significant improvement in the applicability of asynchronous linear solvers as well as in their convergence analysis, and suggests randomization as a key paradigm to serve as a foundation for asynchronous methods.

Managing resources dynamically in hybrid photonic‐electronic networks‐on‐chip

SUMMARYNanophotonics promises to solve the scalability problems of current electrical interconnects thanks to its low sensitivity to distance in terms of latency and energy consumption. Before this technology reaches maturity, hybrid photonic‐electronic networks will be a viable alternative. Ideally, ordinary electrical meshes and ring‐based photonic networks should cooperate to minimize overall latency and energy consumption, but currently, we lack mechanisms to do this efficiently. In this paper, we present novel fine‐grain policies to manage the photonic resources in a tiled chip multiprocessor (CMP) scenario. Our policies are dynamic and base their decisions on parameters such as message size, ring availability, and distance between endpoints, at the message level. The resulting network behavior is also fairer to all cores, reducing processor idle time thanks to faster thread synchronization. All these policies improve performance when compared to the same CMP without the photonic ring, and the most elaborate ones reduce the overall network latency by 50%, execution time by 36%, and network energy consumption by 52% on average, in a 16‐core CMP for the PARSEC benchmark suite. Larger hybrid networks with 64 endpoints for 256‐core CMPs, based on Corona and Firefly designs, also show far superior throughput and lower latency if managed by one of the proposed policies. Copyright © 2014 John Wiley & Sons, Ltd.

A Framework to Analyze the Performance of Load Balancing Schemes for Ensembles of Stochastic Simulations

Ensembles of simulations are employed to estimate the statistics of possible future states of a system, and are widely used in important applications such as climate change and biological modeling. Ensembles of runs can naturally be executed in parallel. However, when the CPU times of individual simulations vary considerably, a simple strategy of assigning an equal number of tasks per processor can lead to serious work imbalances and low parallel efficiency. This paper presents a new probabilistic framework to analyze the performance of dynamic load balancing algorithms for ensembles of simulations where many tasks are mapped onto each processor, and where the individual compute times vary considerably among tasks. Four load balancing strategies are discussed: most-dividing, all-redistribution, random-polling, and neighbor-redistribution. Simulation results with a stochastic budding yeast cell cycle model are consistent with the theoretical analysis. It is especially significant that there is a provable global decrease in load imbalance for the local rebalancing algorithms due to scalability concerns for the global rebalancing algorithms. The overall simulation time is reduced by up to 25 %, and the total processor idle time by 85 %.

Dynamic Voltage Scaling for Real-Time Systems with System Workload Analysis

Dynamic Voltage Scaling (DVS) is a well-known low-power design technique, which adjusts the clock speed and supply voltage dynamically to reduce the energy consumption of real-time systems. Previous studies considered the probabilistic distribution of tasks' workloads to assist DVS in task scheduling. These studies use probability information for intra-task frequency scheduling but do not sufficiently explore the opportunities for the system workload to save more energy. This paper presents a novel DVS algorithm for periodic real-time tasks based on the analysis of the system workload to reduce its power consumption. This algorithm takes full advantage of the probabilistic distribution characteristics of the system workload under priority-driven scheduling such as Earliest-Deadline-First (EDF). Experimental results show that the proposed algorithm reduces processor idle time and spends more busy time in lower-power speeds. The measurement indicates that compared to the relative DVS algorithms, this algorithm saves energy by at least 30% while delivering statistical performance guarantees.

A load-balanced distributed parallel mining algorithm

Due to the exponential growth in worldwide information, companies have to deal with an ever growing amount of digital information. One of the most important challenges for data mining is quickly and correctly finding the relationship among data. The Apriori algorithm has been the most popular technique in finding frequent patterns. However, when applying this method, a database has to be scanned many times to calculate the counts of a huge number of candidate itemsets. Parallel and distributed computing is an effective strategy for accelerating the mining process. In this paper, the Distributed Parallel Apriori (DPA) algorithm is proposed as a solution to this problem. In the proposed method, metadata are stored in the form of Transaction Identifiers (TIDs), such that only a single scan to the database is needed. The approach also takes the factor of itemset counts into consideration, thus generating a balanced workload among processors and reducing processor idle time. Experiments on a PC cluster with 16 computing nodes are also made to show the performance of the proposed approach and compare it with some other parallel mining algorithms. The experimental results show that the proposed approach outperforms the others, especially while the minimum supports are low.

On improving resource utilization and system throughput of master slave job scheduling in heterogeneous systems

The rapid advances of network technologies shed light on many aspects of the practicability of large scale ubiquitous computing. Grid technology has been recognized as an efficient solution to coordinate large-scale shared resources and execute complex applications in heterogeneous network environments. The problem of resource management and task allocation has always been one of the main challenges. In this paper, we present an efficient task allocation strategy for distributing tasks onto computing nodes in the underlying heterogeneous networks. The contribution of the proposed technique is to minimize average turnaround time by dispatching tasks to processors with smallest communication ratio. System throughput could be also enhanced by dispersing processor idle time. The proposed technique can be applied to heterogeneous cluster systems as well as computational grid environments, in which the communication costs vary in different clusters. Experimental results show that the proposed scheme outperforms other previous algorithms in terms of throughput and turnaround time.

Performance effective pre-scheduling strategy for heterogeneous grid systems in the master slave paradigm

It is well known that grid technology has the ability to coordinate shared resources and scheduled tasks. However, the problem of resource management and task scheduling has always been one of the main challenges. In this paper, we present a performance effective pre-scheduling strategy for dispatching tasks onto heterogeneous processors. The main extension of this study is the consideration of heterogeneous communication overheads in grid systems. One significant improvement of our approach is that average turnaround time could be minimized by selecting the processor that has the smallest communication ratio first. The other advantage of the proposed method is that system throughput can be increased by dispersing processor idle time. Our proposed technique can be applied on heterogeneous cluster systems as well as computational grid environments, in which the communication costs vary in different clusters. To evaluate performance of the proposed techniques, we have implemented the proposed algorithms along with previous methods. The experimental results show that our techniques outperform other algorithms in terms of lower average turnaround time, higher average throughput, less processor idle time and higher processors’ utilization.

A parallel, incremental, mostly concurrent garbage collector for servers

Multithreaded applications with multigigabyte heaps running on modern servers provide new challenges for garbage collection (GC). The challenges for “server-oriented” GC include: ensuring short pause times on a multigigabyte heap while minimizing throughput penalty, good scaling on multiprocessor hardware, and keeping the number of expensive multicycle fence instructions required by weak ordering to a minimum.We designed and implemented a collector facing these demands building on the mostly concurrent garbage collector proposed by Boehm et al. [1991]. Our collector incorporates new ideas into the original collector. We make it parallel and incremental; we employ concurrent low-priority background GC threads to take advantage of processor idle time; we propose novel algorithmic improvements to the basic mostly concurrent algorithm improving its efficiency and shortening its pause times; and finally, we use advanced techniques, such as a low-overhead work packet mechanism to enable full parallelism among the incremental and concurrent collecting threads and ensure load balancing.We compared the new collector to the mature, well-optimized, parallel, stop-the-world mark-sweep collector already in the IBM JVM. When allowed to run aggressively, using 72% of the CPU utilization during a short concurrent phase, our collector prototype reduces the maximum pause time from 161 ms to 46 ms while only losing 11.5% throughput when running the SPECjbb2000 benchmark on a 600-MB heap on an 8-way PowerPC 1.1-GHz processors. When the collector is limited to a nonintrusive operation using only 29% of the CPU utilization, the maximum pause time obtained is 79 ms and the loss in throughput is 15.4%.

Performance analysis tools applied to a finite element adaptive mesh free boundary seepage parallel algorithm

A finite element, adaptive mesh, free surface seepage parallel algorithm is studied using performance analysis tools in order to optimize its performance. The physical problem being solved is a free boundary seepage problem which is nonlinear and whose free surface is unknown a priori. A fixed domain formulation of the problem is discretized and the parallel solution algorithm is of successive over-relaxation type. During the iteration process there is message-passing of data between the processors in order to update the calculations along the interfaces of the decomposed domains. A key theoretical aspect of the approach is the application of a projection operator onto the positive solution domain. This operation has to be applied at each iteration at each computational point.The VAMPIR and PARAVER performance analysis software are used to analyze and understand the execution behavior of the parallel algorithm such as: communication patterns, processor load balance, computation versus communication ratios, timing characteristics, and processor idle time. This is all done by displays of post-mortem trace-files. Performance bottlenecks can easily be identified at the appropriate level of detail. This will numerically be demonstrated using example test data and comparisons of software capabilities that will be made using the Blue Horizon parallel computer at the San Diego Supercomputer Center.

Synchroscalar

We present Synchroscalar, a tile-based architecture forembedded processing that is designed to provide the flexibilityof DSPs while approaching the power efficiency ofASICs. We achieve this goal by providing high parallelismand voltage scaling while minimizing control and communicationcosts. Specifically, Synchroscalar uses columnsof processor tiles organized into statically-assignedfrequency-voltage domains to minimize power consumption.Furthermore, while columns use SIMD control to minimizeoverhead, data-dependent computations can besupported by extremely flexible statically-scheduled communicationbetween columns.We provide a detailed evaluation of Synchroscalar includingSPICE simulation, wire and device models, synthesisof key components, cycle-level simulation, andcompiler- and hand-optimized signal processing applications.We find that the goal of meeting, not exceeding, performancetargets with data-parallel applications leads todesigns that depart significantly from our intuitions derivedfrom general-purpose microprocessor design. Inparticular, synchronous design and substantial global interconnectare desirable in the low-frequency, low-powerdomain. This global interconnect supports parallelizationand reduces processor idle time, which are critical to energyefficient implementations of high bandwidth signalprocessing. Overall, Synchroscalar provides programmabilitywhile achieving power efficiencies within 8-30X ofknown ASIC implementations, which is 10-60X better thanconventional DSPs. In addition, frequency-voltage scalingin Synchroscalar provides between 3-32% power savingsin our application suite.

Local grid scheduling techniques using performance prediction

The use of computational grids to provide an integrated computer platform, composed of differentiated and distributed systems, presents fundamental resource and workload management questions. Key services such as resource discovery, monitoring and scheduling are inherently more complicated in a grid environment where the resource pool is large, dynamic and architecturally diverse. The authors approach the problem of grid workload management through the development of a multi-tiered scheduling architecture (TITAN) that employs a performance prediction system (PACE) and task distribution brokers to meet user-defined deadlines and improve resource usage efficiency. Attention is focused on the lowest tier which is responsible for local scheduling. By coupling application performance data with scheduling heuristics, the architecture is able to balance the processes of minimising run-to-completion time and processor idle time, whilst adhering to service deadlines on a per-task basis.

The VAMPIR and PARAVER performance analysis tools applied to a wet chemical etching parallel algorithm

A wet chemical etching parallel algorithm is studied using performance analysis tools in order to optimize its performance. The physical problem being solved is a moving boundary problem which is nonlinear and whose etching front is unknown a priori at each time. A fixed domain formulation of the problem is discretized and the parallel solution algorithm is of successive over-relaxation type. During the iteration process there is message-passing of data between the processors in order to update the calculations along the interfaces of the decomposed domains. A key theoretical aspect of the approach is the application of a projection operator onto the positive solution domain. This operation has to be applied at each iteration at each computational point. The VAMPIR and PARAVER performance analysis software are used to analyze and understand the execution behavior of the parallel algorithm such as: communication patterns, processor load balance, computation versus communication ratios, timing characteristics, and processor idle time. This is all done by displays of post-mortem trace-tiles. Performance bottlenecks can easily be identified at the appropriate level of detail. This will numerically be demonstrated using example test data and comparisons of software capabilities will be made using the Blue Horizon parallel computer at the San Diego

Parallel ADI solver based on processor scheduling

Gaussian elimination is used for the direct solution of banded linear systems that typically appear in implicit numerical methods for PDEs. Gaussian elimination for narrow-banded systems (also known as the Thomas algorithm (TA)) includes forward and backward recurrences along lines of a numerical grid. Multi-domain decomposition, essential for parallelization of implicit solvers, spans the recurrences across processors in one or more directions. Processor idle time and inter-processor communication time are two interdependent reasons for the poor parallelization efficiency of TAs. In this research an efficient parallel algorithm for 3D directionally split problems is developed. The proposed solver is based on the static scheduling of processors where local and non-local, data-dependent and data-independent computations are scheduled while processors are idle. The proposed algorithm uses a reformulated version of the pipelined Thomas algorithm that starts the backward step computations immediately after the completion of the forward step computations for the first portion of lines. This algorithm has data available for other computational tasks while processors are idle from the TA. A theoretical model of parallelization efficiency is used to define optimal parameters of the algorithm, to show an asymptotic parallelization penalty and to obtain an optimal cover of a global domain with subdomains. It is shown by computational experiments and by the theoretical model that the proposed algorithm considerably reduces the communication cost and processor idle time over the basic algorithm for the range of the number of processors (subdomains) considered and the number of grid nodes per subdomain.

A parallel, incremental and concurrent GC for servers

Multithreaded applications with multi-gigabyte heaps running on modern servers provide new challenges for garbage collection (GC). The challenges for "server-oriented" GC include: ensuring short pause times on a multi-gigabyte heap, while minimizing throughput penalty, good scaling on multiprocessor hardware, and keeping the number of expensive multi-cycle fence instructions required by weak ordering to a minimum. We designed and implemented a fully parallel, incremental, mostly concurrent collector, which employs several novel techniques to meet these challenges. First, it combines incremental GC to ensure short pause times with concurrent low-priority background GC threads to take advantage of processor idle time. Second, it employs a low-overhead work packet mechanism to enable full parallelism among the incremental and concurrent collecting threads and ensure load balancing. Third, it reduces memory fence instructions by using batching techniques: one fence for each block of small objects allocated, one fence for each group of objects marked, and no fence at all in the write barrier. When compared to the mature well-optimized parallel stop-the-world mark-sweep collector already in the IBM JVM, our collector prototype reduces the maximum pause time from 284 ms to 101 ms, and the average pause time from 266 ms to 66 ms while only losing 10% throughput when running the SPECjbb2000 benchmark on a 256 MB heap on a 4-way 550 MHz Pentium multiprocessor.