Processing Application Specific Integrated Circuit Research Articles

The design and development of low- and high-voltage ASICs for space-borne CCD cameras

The CCD remains the pre-eminent visible and UV wavelength image sensor in space science, Earth and planetary remote sensing. However, the design of space-qualified CCD readout electronics is a significant challenge with requirements for low-volume, low-mass, low-power, high-reliability and tolerance to space radiation. Space-qualified components are frequently unavailable and up-screened commercial components seldom meet project or international space agency requirements. In this paper, we describe an alternative approach of designing and space-qualifying a series of low- and high-voltage mixed-signal application-specific integrated circuits (ASICs), the ongoing development of two low-voltage ASICs with successful flight heritage, and two new high-voltage designs. A challenging sub-system of any CCD camera is the video processing and digitisation electronics. We describe recent developments to improve performance and tolerance to radiation-induced single event latchup of a CCD video processing ASIC originally developed for NASA’s Solar Terrestrial Relations Observatory and Solar Dynamics Observatory. We also describe a programme to develop two high-voltage ASICs to address the challenges presented with generating a CCD’s bias voltages and drive clocks. A 0.35 μm, 50 V tolerant, CMOS process has been used to combine standard low-voltage 3.3 V transistors with high-voltage 50 V diffused MOSFET transistors that enable output buffers to drive CCD bias drains, gates and clock electrodes directly. We describe a CCD bias voltage generator ASIC that provides 24 independent and programmable 0–32 V outputs. Each channel incorporates a 10-bit digital-to-analogue converter, provides current drive of up to 20 mA into loads of 10 μF, and includes current-limiting and short-circuit protection. An on-chip telemetry system with a 12-bit analogue-to-digital converter enables the outputs and multiple off-chip camera voltages to be monitored. The ASIC can drive one or more CCDs and replaces the many discrete components required in current cameras. We also describe a CCD clock driver ASIC that provides six independent and programmable drivers with high-current capacity. The device enables various CCD clock parameters to be programmed independently, for example the clock-low and clock-high voltage levels, and the clock-rise and clock-fall times, allowing configuration for serial clock frequencies in the range 0.1–2 MHz and image clock frequencies in the range 10–100 kHz. Finally, we demonstrate the impact and importance of this technology for the development of compact, high-performance and low-power integrated focal plane electronics.

Design of a video capsule endoscopy system with low-power ASIC for monitoring gastrointestinal tract.

In recent years, wireless capsule endoscopy (WCE) has been a state-of-the-art tool to examine disorders of the human gastrointestinal tract painlessly. However, system miniaturization, enhancement of the image-data transfer rate and power consumption reduction for the capsule are still key challenges. In this paper, a video capsule endoscopy system with a low-power controlling and processing application-specific integrated circuit (ASIC) is designed and fabricated. In the design, these challenges are resolved by employing a microimage sensor, a novel radio frequency transmitter with an on-off keying modulation rate of 20Mbps, and an ASIC structure that includes a clock management module, a power-efficient image compression module and a power management unit. An ASIC-based prototype capsule, which measures Φ11mm×25mm, has been developed here. Test results show that the designed ASIC consumes much less power than most of the other WCE systems and that its total power consumption per frame is the least. The image compression module can realize high near-lossless compression rate (3.69) and high image quality (46.2dB). The proposed system supports multi-spectral imaging, including white light imaging and autofluorescence imaging, at a maximum frame rate of 24fps and with a resolution of 400×400. Tests and in vivo trials in pigs have proved the feasibility of the entire system, but further improvements in capsule control and compression performance inside the ASIC are needed in the future.

A wireless capsule system with ASIC for monitoring the physiological signals of the human gastrointestinal tract.

This paper presents the design of a wireless capsule system for monitoring the physiological signals of the human gastrointestinal (GI) tract. The primary components of the system include a wireless capsule, a portable data recorder, and a workstation. Temperature, pH, and pressure sensors; an RF transceiver; a controlling and processing application specific integrated circuit (ASIC); and batteries were applied in a wireless capsule. Decreasing capsule size, improving sensor precision, and reducing power needs were the primary challenges; these were resolved by employing micro sensors, optimized architecture, and an ASIC design that include power management, clock management, a programmable gain amplifier (PGA), an A/D converter (ADC), and a serial peripheral interface (SPI) communication unit. The ASIC has been fabricated in 0.18- μm CMOS technology with a die area of 5.0 mm × 5.0 mm. The wireless capsule integrating the ASIC controller measures Φ 11 mm × 26 mm. A data recorder and a workstation were developed, and 20 cases of human experiments were conducted in hospitals. Preprocessing in the workstation can significantly improve the quality of the data, and 76 original features were determined by mathematical statistics. Based on the 13 optimal features achieved in the evaluation of the features, the clustering algorithm can identify the patients who lack GI motility with a recognition rate reaching 83.3%.

A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC

This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.

ASIC by Design - Automated design of digital signal processing application-specific integrated circuits

Comparing the optimized results to the baseline, we are achieving typically 10-20/spl times/ improvement in PDA. This allows gap closure to approach the optimization of a full custom design process while preserving the automation and design efficiency of ASIC design. Additionally, the reuse of each macro saves two to three staff-months, and each optimization script saves one to two staff-months. Hence, we achieve an overall reduction in design time even though it takes extra time to run these optimization tools. The mission-specific processing (MSP) design flow can be applied to a wide range of DSP and other digital processing applications, where high performance and integration is required. The macros developed were selected to span important algorithms commonly performed in communication, radar, navigation, targeting, electronic warfare and other military and national security applications.

A signal processing ASIC for ISFET-based chemical sensors

With the advantages of small size, reliability, rapid response, compatibility to standard CMOS technology and on-chip signal processing, Ion-Sensitive Field Effect Transistor (ISFET)-based transducers are increasingly being applied in physiological data acquisition and environment monitoring. This paper presents a signal processing Application Specific Integrated Circuit (ASIC) and a discrete temperature compensation chip design of a potentiometric ISFET-based chemical sensor. To assure the measurement of a correct pH value, the two-point calibration circuitry based on the response of standard pH 4 and 7 buffer solution has been implemented by using Algorithmic State Machine hardware algorithms. For battery power consideration, the proposed signal processing ASIC consisting of low voltage (3 V) mixed signal modules has been developed and fabricated in a 0.5 μm CMOS technology. The results demonstrate small differences of pH response of ISFET's operating with and without ASIC device, i.e. only the order of 0.1 mV/pH with respect to sensitivity. Furthermore, using the temperature compensating circuitry reduces the ISFET temperature coefficient to +0.15 mV/°C, and hence results in a lower pH value variation of −0.0023 pH/°C. It was shown that more accurate pH measurement can be concluded with the proposed ASIC and V T extractor circuitry.

A bit-serial first-level calorimeter trigger for an LHC detector

A preliminary design of a compact first-level calorimeter trigger, implemented as a farm of local bit-serial systolic arrays, is presented. The bit-serial data representation allows higher processing rates and more compact designs than are possible when using parallel data. More functionality can be incorporated into the Application Specific Integrated Circuits (ASICs) that serve as the main processing elements. The trigger processor seeks local energy clusters, evaluates isolation criteria within the electromagnetic calorimeter and leakage into the hadron calorimeter in order to detect electrons. It uses cluster finding algorithms to identify jets and missing transverse energy to estimate neutrino energies. The processor output serves as decision support for the central first-level trigger and delivers region-of-interest positions to the second-level trigger. In its present form the trigger processor design relies on optical fibers to deliver the input data from the front-end modules and multi-chip modules (MCMs) to harbor the processing ASICs. The fact that the main part of the trigger processor can fit into one or two large crates suggests that the design is not limited by size nor is it strictly limited by cost but can be expanded to accommodate extended algorithms if these are found necessary. Extensive physics simulations will explore these possibilities.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>