Selective Growth Process Research Articles

Selective Epitaxial Growth of SiGe(:B) for Advanced p-Type Fd-SOI

We focus here on various Selective Epitaxial Growth (SEG) processes used during the manufacturing of advanced p-MOSFET devices: (i) 20 nm thick in-situ boron doped Si0.7Ge0.3 layers grown at 650 °C, 20 Torr then capped with 5 nm of Si:B (at 730 °C, 20 Torr) for Raised Sources and Drains (RSDs) and (ii) 8 nm intrinsic SiGe layers grown at 650–700 °C, 20 Torr for channels. Those layers were grown with a heavily chlorinated chemistry to maintain full selectivity versus SiN hard-mask or SiCO sidewall spacers. The impact of diborane, germane and hydrochloric acid mass-flows on growth kinetics and doping were first of all quantified on blanket wafers. Epitaxial processes were optimized in terms of (i) doping and growth rates, which should be as high as possible while still having superior structural and electrical properties and (ii) selectivity against dielectrics. In a second part, we highlight some of difficulties encountered when switching to patterned substrates. The morphology, faceting and loading effects in such layers are discussed.

A Photolithography-Free Fabrication Strategy for Perovskite Photodetector Array with High-Security Imaging Application.

Metal halide perovskites have attracted significant attention for high-performance and cost-effective photodetector (PD) arrays in recent years. Traditional perovskite photodetector arrays typically rely on planar structure and photolithography, which limit resolution and involve complex, costly processes. To address these challenges, an innovative, lithography-free fabrication strategy is proposed utilizing direct laser writing ablation and a surface energy-assisted selective growth process. A 10×10 self-powered perovskite photodetector array is demonstrated with a vertical cross-bar structure fabricated on a laser-ablated textured Indium-Tin Oxide (ITO) substrate which improves the device performance. The device exhibits a fast photoresponse and effective imaging capability. Moreover, the intrinsic physical disorder and randomness of perovskite provide highly secure entropy sources, making the photodetector array suitable for physical unclonable function (PUF) devices. This method offers a promising opportunity for simplifying the fabrication process, enhancing manufacturability, and advancing the application of perovskite PD arrays in secure imaging systems.

In Situ Creation of Surface Defects on Pd@NiPd with Core-shell Hierarchical Structure Toward Boosting Electrocatalytic Activity.

A deep insight into surface structural evolution of the catalyst is a challenging issue to reveal the structure-activity relationship. In this contribution, based on a surface alloying strategy, the dual-functional Pd@NiPd catalyst with a unique core-shell hierarchical structure is developed through selective crystal growth, surface cocrystallization, directional self-assembly, and reduction process. The surface defects are created in situ on the outer NiPd alloy layer in the electrochemical redox processes, which endow the Pd@NiPd catalyst with excellent electrocatalytic activity of hydrogen generation reaction (HER) and oxygen generation reaction (OER) in alkaline media. The optimal Pd@NiPd-2 catalyst requires an overpotential of only 18 mV that is far lower than Pt/C benchmark (43 mV) at the current density of 10 mA cm-2 for the HER, and 210 mV that is far lower than RuO2 benchmark (430 mV) at 50 mA cm-2 for the OER. Density functional theory (DFT) calculations reveal that the outstanding electrocatalytic activity is originated from the creation of surface defect structure that induces a significant reduction in the adsorption and dissociation energy barriers of H2O molecules in the HER and a decrease in the conversion energy from O* to OOH* that resulted from the synergy of two adjacent Pd sites by forming O-bridge. This work affords a typical paradigm for exploiting efficient catalysts and investigating the dependence of electrocatalytic activity on the surface structural evolution.

Leveraging the 1,3-azadiene-anhydride reaction for the synthesis of functionalized piperidines bearing up to five contiguous stereocenters.

A modular and scalable strategy, which remodels 3-methylglutaric anhydride to 2-oxopiperidines bearing at least three contiguous stereocenters is described. The approach relies on the chemoselective and stereocontrolled annulation of 1,3-azadienes with the anhydride component. The resulting acid-tethered allylic 2-oxopiperidines are then engaged in several selective fragment growth processes, including catalytic denitrative alkenylation, halolactonization, and Vilsmeier–Haack functionalization.

Selective growth and upconversion photoluminescence of Y-based fluorides: from NaYF4: Yb/Er to YF3: Yb/Er crystals

Y-based fluorides have been recognized as most efficient host materials for upconversion photoluminescence (UC-PL). Herein, we have produced a series of Yb/Er doped Y-based fluorides with specific crystal structures, shapes and sizes. The selective growth process is governed by our pre-designed surfactant 4, 4′-((2,5-bi’s (2-(diethylamino) ethoxy) −1,4-phenylene) bis (ethyne-2,1-diyl)) dibenzoic acid (DBA) and selective solvents. It is shown that highly pure hexagonal microprisms and cubic microspheres of NaYF4: Yb/Er could be selectively grown in water at low and high content of DBA, respectively, while only orthorhombic nanowires and microflowers of YF3: Yb/Er could be obtained in ethanol. Finally, all these materials obtained exhibit strong UC-PL signal while the UC emission intensity of the NaYF4: Yb/Er hexagonal microprisms is much higher than those of the cubic microspheres and orthorhombic YF3 nanowires and microflowers. This work provides a novel method for selective crystal growth of Y-based fluorides with specific shape, size, crystal phase and highly UC-PL efficiency by breaking the intrinsic limitation of crystal growth habit, which could be possibly extended to the controlled synthesis of other related materials.

Quantum Transport in Topological Surface States of Selectively Grown Bi2Te3 Nanoribbons

AbstractQuasi‐1D nanowires of topological insulators are candidate structures in superconductor hybrid architectures for Majorana fermion based quantum computation schemes. Here, selectively grown Bi2Te3 topological insulator nanoribbons at cryogenic temperatures are investigated. The nanoribbons are defined in deep‐etched Si3N4/SiO2 nano‐trenches on a silicon (111) substrate followed by a selective area growth process via molecular beam epitaxy. The selective area growth is beneficial to the device quality, as no subsequent fabrication needs to be performed to shape the nanoribbons. In the diffusive transport regime of these unintentionally n‐doped Bi2Te3 topological insulator nanoribbons, electron trajectories are identified by analyzing angle dependent universal conductance fluctuation spectra. When the sample is tilted from a perpendicular to a parallel magnetic field orientation, these high frequent conductance modulations merge with low frequent Aharonov–Bohm type oscillations originating from the topologically protected surface states along the nanoribbon perimeter. For 500 nm wide Hall bars low frequent Shubnikov–de Haas oscillations are identified in a perpendicular magnetic field orientation. These reveal a topological, high‐mobility, 2D transport channel, partially decoupled from the bulk of the material.

Abnormal Silicon-Germanium (SiGe) Epitaxial Growth in FinFETs

In an advanced complementary metal-oxide-semiconductor (CMOS) technology node, small nano-scopic defects tend to have a significant impact on the yield and reliability of the final product. As the technology advances in fin field-effect-transistors (FinFETs), it has become increasingly challenging to control the extent of defects while also ensuring that the desired processing parameters are in place. The process of selective epitaxial growth of silicon-germanium (SiGe) on source/drain (S/D) regions is especially prone to defects due to the complexity of the process, thus giving a very narrow processing window to achieve the desired device, yield and reliability results. In this paper we evaluate a critical defect of “Abnormal epi” seen during the selective epitaxial growth of in-situ boron (B) doped SiGe on FinFETs. Abnormal epi here refers to abnormally large and spurious epitaxial growth defect occurring as random instances on a wafer die. These defects, depending on where in the layout they occur, can lead to catastrophic failure under higher test voltages due to the physical shorting of n and p FET devices. We also explore the process parameters which influence this defect including incoming surface conditions and propose mechanisms that lead to the defect. Further, an optimization of the processing parameters in the integration scheme to minimize the occurrence of these defects leads to yield gain and cost savings required for high volume manufacturing.

Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device

In this work, SiGe Fin formation technique using shallow trench isolation (STI) first or STI last strategy for the high mobility channel FinFET device is systematically investigated. A 20 nm width and 35 nm height high crystalline quality of the Si0.7Ge0.3 Fin formation for STI first scheme is demonstrated by utilizing a new developed Si Fin etching, Si Fin recess and SiGe selective epitaxial growth process. For the STI last strategy, a novel chemical mechanical planarization (CMP) treated three-layer SiGe strain relaxed buffer (SRB) is successfully fabricated and a 50 nm high crystal quality and atomically smooth surface Si0.5Ge0.5 layer on this SRB is attained. Moreover, a spike annealing is employed to avoid the Si0.5Ge0.5 Fin oxidation during STI densification with an acceptable STI etching rate. However, both a spike annealing and a lower temperature of traditional furnace at 850 °C or 750 °C suffer micro-trench issue during the Fin reveal process. Therefore, a new developed process, named as STI recess first, is developed to resolve both thermal instability and micro-trench issue at the same time. A minor Si0.5Ge0.5 Fin loss with a sharp Si0.7Ge0.3 SRB/Si0.5Ge0.5 interfaces for STI last scheme is realized by utilizing this new developed STI recess first process.

(Invited) Expanding the Toolbox of Atomic Scale Processing: From Materials Control to Selective Processing By Plasma ALD

As we enter an era of atomic scale devices,1 there is a strict need for precise control over the thickness and properties of materials employed in device fabrication.2,3 Furthermore, next-generation device architectures consist of various material layers with dielectric or conductive properties on planar and three-dimensional (3D) features. This has led to an additional need for expanding the toolbox of atomic scale processing techniques – such as atomic layer deposition (ALD) and atomic layer etching (ALE) – with new approaches in selective processing.2,3,4 As early as 1990, different categories of selectivity during film growth on a patterned planar substrate (composed of different surface materials) have been defined in the literature in terms of area-, phase-, microstructure or chemical composition-selective deposition.5 The last three categories have been defined based on the inherent differences in material properties ensuing from simultaneous growth on a patterned substrate. As a result, these cases are simply different examples of one common selective growth process, namely material property-selective deposition. Plasma-enhanced atomic layer deposition (ALD) is a technique that uses the reactive species generated in a plasma (i.e. radicals, ions) for growing materials with atomic scale precision. In this work, we will demonstrate how plasma ALD can open new avenues for controlling material properties and carrying out selective processing on both planar and 3D substrates. We will show how plasma ALD can yield simultaneous growth of the same material with different properties (e.g. phase-selective deposition) on a patterned substrate. We will then demonstrate how implementing ion energy control during plasma ALD can enhance the versatility of this processing technique by enabling accurate control over a wide range of material properties during deposition.6,7 And finally, we will show how controlling ion energies during plasma ALD on 3D trench-shaped nanostructures can provide an alternate route for topographically selective materials processing,6 relevant for next-generation device fabrication.3,4 1 Salahuddin et al., Nat. Electron. 1, 442-450 (2018) 2 Knoops et al., J. Vac. Sci. Technol. A 37, 030902 (2019) 3 Faraz et al., ECS J. Solid State Sci. Technol. 4, N5023-N5032 (2015) 4 Clark et al., APL Mater. 6, 058203 (2018) 5 Carlsson, Crit. Rev. Solid State Mater. Sci. 16, 161-212 (1990) 6 Faraz et al., ACS Appl. Mater. Interfaces 10, 13158-13180 (2018) 7 Faraz et al., Plasma Sources Sci. Technol. 28, 024002 (2019) Figure 1

Schottky barrier diode fabricated on oxygen-terminated diamond using a selective growth approach

A Schottky barrier diode (SBD) fabricated on oxygen-terminated diamond using a selective growth approach is demonstrated. Patterned tungsten (W) film was used as the mask, and ohmic contact was formed between W and diamond during the selective growth process. After growth, the selective epitaxial diamond surface was treated by UV-ozone to achieve oxygen termination. Then, Zr/Ni/Au Schottky electrode was patterned on the selective grown diamond surface. The I-V characteristics indicate that the SBD is p-type, and a rectification ratio of more than 5 orders of magnitude at ±20 V at room temperature is observed. The acceptor might be introduced by W incorporated into diamond during selective growth process, and its concentration was determined to be 2.7 × 1014 cm−3 from C−2-V curve. The reverse breakdown voltage of the SBD is 1316 V, corresponding to a breakdown electrical field of 6.3 MV/cm. The reverse current-voltage characteristics show that the UV ozone treatment can favorably suppress reverse leakage current.

Application of Cl2 for low temperature etch and epitaxy

In this work, two most typical applications of Cl2 etch relevant for sub-10 nm CMOS device production, namely sacrificial etch and selective deposition are presented. It is shown that Si0.7Ge0.3 sacrificial etch with Cl2 is possible in the temperature range of 350 °C–400 °C when He is used as a carrier gas. This temperature range can be further lowered when He is substituted with N2. Use of N2 also allows Si etch at very low temperatures (∼400 °C) which are not accessible for etching with HCl and potentially can be used for sacrificial etch of Si and Si-based epitaxial selective growth processes. Furthermore, a combination of Cl2 with high order Si and Ge precursors allowed development of cyclic selective epitaxial processes at temperatures as low as 400 °C with active dopant concentrations of ∼1 × 1020 cm−3 for Si0.7Ge0.3:B and ∼3 × 1019 cm−3 for Si0.7Ge0.3:P.

An electrically injected AlGaN nanowire defect-free photonic crystal ultraviolet laser.

We report on the demonstration of an electrically injected AlGaN nanowire photonic crystal laser that can operate in the ultraviolet spectral range. The nanowire heterostructures were grown on sapphire substrate using a site-controlled selective area growth process. By exploiting the topological high-Q resonance of a defect-free nanowire photonic crystal, we have demonstrated electrically pumped lasers that can operate at 369.5 nm with a relatively low threshold current density of ~2.1 kA/cm2 under continuous wave operation at room-temperature. This work provides a promising approach for achieving low threshold semiconductor laser diodes operating in the UV spectral range that were previously difficult.

Core-shell p-i-n GaN nanowire LEDs by N-polar selective area growth.

GaN nanowire LEDs with radial p-i-n junctions were grown by molecular beam epitaxy using N-polar selective area growth on Si(111) substrates. The N-polar selective area growth process facilitated the growth of isolated and high-aspect-ratio n-type NW cores that were not subject to self-shadowing effects during the subsequent growth of a conformal low-temperature Mg:GaN shell. LED devices were fabricated from single-NW and multiple-NW arrays in their as-grown configuration by contacting the n-type core through an underlying conductive GaN layer and the p-type NW shell via a metallization layer. The NW LEDs exhibited rectifying I-V characteristics with a sharp turn-on voltage near the GaN bandgap and low reverse bias leakage current. Under forward bias, the NW LEDs produced electroluminescence with a peak emission wavelength near 380 nm and exhibited a small spectral blueshift with increasing current injection, both of which are consistent with electron recombination in the p-type shell layer through donor-acceptor-pair recombination. These core-shell NW devices demonstrate N-polar selective area growth as an effective technique for producing on-chip nanoscale light sources.

(Invited) Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in Finfet, Stacked Nanowires and Monolithic 3D Integration

Microelectronic devices enable the continuous improvement in mobile data exchange and mobile communication. This exciting technological progress has been achieved by transistor scaling, resulting in an increased performance for lower energy consumption and cost. As CMOS device scaling proceeds, the number of epitaxial growth steps in device fabrication schemes increases. Examples are SiGe or Ge as high mobility channel materials [1-3], SiGe/Si or SiGe/Ge multi-layers to define nanowires in lateral Gate All Around (GAA) devices [3-5], and Source/Drain (S/D) stressor layers which also allow to reduce the S/D contact resistance [3,6-8]. In this contribution we will describe the characteristics of the epitaxial growth schemes as used for Fin and Gate-All-Around (GAA) devices. For Si- and SiGe-channel GAA devices, strained SiGe/Si multi-layers, which are used to define lateral nanowires, can be grown with conventional precursors (SiH4 or SiCl2H2 and GeH4). The compositional gradient is sufficiently steep to allow efficient wire release by selective SiGe or Si removal [2,5,9]. In case of Ge GAA, epitaxial growth of Ge-rich SiGe/Ge on SiGe Strain Relaxed Buffers is more challenging. Extremely low process temperatures are required to avoid strain relaxation. These layers need to be grown with higher order precursors, since conventional precursors become ineffective [4]. The epitaxial growth of ultra-thin Si layers on (strained) Ge fins or lateral nanowires used to passivate Ge surfaces in the high-k gate module has been discussed at the ECS Fall meeting of 2017 [10] and will not be covered in this presentation. A major challenge is to increase the active doping concentration in epitaxial S/D layers. Current scaling of gate and fin pitch reduces contact area and the contact resistance becomes a key contributor to device parasitics [7,11]. In addition, monolithic 3D integration, requires to reduce the thermal budget of the complete epitaxial growth scheme (including pre-epi surface cleaning). For Si:P, we demonstrated that P doping activation can be increased by post-epi anneals (>1e21 cm-3) without major strain loss [8]. Nearly similar active doping concentrations (up to 8e20 cm-3) are obtained by using Si3H8 instead of SiCl2H2 and low growth temperatures without the need for a post epi thermal treatment. For SiGe:B, we obtained similar active boron concentrations using conventional precursors [12,13]. Because of the low boron solubility in Ge, it is more challenging to fabricate S/D Ge pMOS contacts with the right lattice constant (to act as a stressor) and with a sufficiently high active doping concentration. Effort is ongoing to increase the active boron concentration by moving the growth process further away from equilibrium. This is done at low growth temperatures by either using Ge2H6 as high-order precursor or by assessing new materials such as GeSn. On blanket wafers, higher active doping concentrations have been reported but it is extremely challenging to translate this into a selective growth process without Sn precipitation. This triggered the research community to assess alternative dopants. For Ge, the Ga doping solubility is significantly higher than that of B. Epitaxial growth schemes are preferred above ion implantation as the latter one requires an unwanted high thermal budget for doping activation and on patterned wafers it does not allow conformal doping profiles. First Ge:Ga layers with a resistivity below 0.4 mΩ.cm have been grown without any detectable C incorporation. In addition, Ga + B co-doping enables to reduce the resistivity of SiGe:B:Ga, which confirms the potential of Ga as an add-on. Acknowledgements The imec core CMOS program members, European Commission, the TAKEMI5 ECSEL project, local authorities and the imec pilot line are acknowledged for their support. Air Liquide Advanced Materials is acknowledged for providing advanced precursor gases.

Synthesis, Formation Mechanism, and Magnetic Properties of Monodisperse Semiconducting Spinel CdCr2S4 Nanocrystals via a Facile “Seed-Mediated” Growth Method

The chalcogenide spinel CdCr2S4 is a well-established ferromagnetic semiconductor that exhibits unique properties and is a promising candidate for spintronic applications. With band gap in the visible wavelength region, CdCr2S4 nanocrystals offer the exciting possibility of tailoring both the optical and magnetic properties with precise morphology control. However, the synthesis of monodisperse CdCr2S4 nanocrystals is challenging and has not been reported. A unique “seed-mediated” growth process has been developed for the synthesis that involves using cubic-phase CdS, which has a face-centered cubic crystal structure similar to that of CdCr2S4, as a “seed” to react with CrCl3·6H2O in a solution mixture of 1-dodecanethiol and 1-octadecene. Remarkably, hexagonal-phase CdS is ineffective as a “seed” for formation of the desired product. A mechanism for formation of monodisperse CdCr2S4 nanocrystals by the selective growth process is proposed, and the structural and magnetic properties of the synthesized nanocrystals are presented. The novel synthetic strategy can be exploited for the controlled formation of other complex magnetic chalcogenides.

Mechanism for selective growth in electrical steel

Through the competitive selective growth process between {100}, {110}, and {111} grains during final annealing which is governed by the primary grain size and the surface segregation concentration of sulfur, the sharp {110} annealing texture can be developed in a C-and Al-free Fe-3%Si-0.1%Mn electrical steel. Generally, the selective growth of the {110} grains occurs actively under the low surface segregation concentration of sulfur. In spite of the surface energy disadvantage, the selective growth of a {hkl} grain can however occur, if the {hkl} grain size is larger than the critical grain size linearly proportional to the strip thickness.

Selective epitaxial growth properties and strain characterization of Si1−x Ge x in SiO2 trench arrays

In this study, we investigated the formation of a Si1−xGex fin structure in SiO2 trench arrays via an ultra-high-vacuum chemical-vapor deposition (UHV-CVD) selective epitaxial growth (SEG) process. Defect generation and microstructures of Si1−xGex fin structures with different Ge concentrations (x = 0.2, 0.3 and 0.45) were examined. In addition, the strain evolution of a Si1−xGex fin structure was analyzed by using reciprocal space mapping (RSM). An (111) facet was formed from the Si1−xGex epi-layer and SiO2 trench wall interface to minimize the interface and the surface energy. The Si1−xGex fin structures were fully relaxed along the direction perpendicular to the trenches regardless of the Ge concentration. On the other hand, the fin structures were fully or partially strained along the direction parallel to the trenches depending on the Ge concentration: fully strained Si0.8Ge0.2 and Si0.7Ge0.3, and a Si0.55Ge0.45 strain-relaxed buffer. We further confirmed that the strain on the Si1−xGex fin structures remained stable after oxide removal and H2/N2 post-annealing.

Position controlled and seed/catalyst free growth of ZnO nanorod arrays on reduced graphene oxide nanosheets

A new type of seed/catalyst-free and selective-growth process is developed for in situ grown vertically-aligned ZnO nanorods on the reduced graphene oxide (rGO) nanosheets. The dense and single-crystalline ZnO nanorods have been successfully grow on rGO nanosheets with the position- and size-controlled. The effect of rGO layer on the ZnO nanorods and the growth mechanism were investigated. The position of ZnO nanorod arrays correlates well with the size and position of rGO nanosheets, which is determined by dangling bonds such as oxygen-containing groups on rGO surface. Meanwhile, ZnO nanorods could grow laterally to form a continuous arrays with a large coverage on rGO substrates, which is mainly due to the step edges in rGO boundaries. The diameter and density of ZnO nanorods were readily determined by the growth temperature, and the length was easily controlled by the growth time. The absorption and PL spectrums suggest that ZnO nanorods/rGO have a strong UV absorption ranging from 330 to 375 nm and no obvious UV PL emission at room temperature, which indicates that the ZnO nanorods/rGO nanohybrids could be an excellent candidate for application in UV photodetectors. This work represents the success in seed/catalyst-free fabrication of aligned ZnO nanorod arrays directly on rGO nanosheets and the process can be readily scaled up for industrial applications of optoelectronic devices.

Seed/Catalyst Free Growth and Self-Powered Photoresponse of Vertically Aligned ZnO Nanorods on Reduced Graphene Oxide Nanosheets

The seed/catalyst-free and selective-growth process is developed for in situ grown single-crystalline and vertically aligned ZnO nanorods on the reduced graphene oxide (rGO) nanosheets. In this process, the position of ZnO nanorod arrays correlates well with the size and position of rGO nanosheets, which is strongly depended on both dangling bonds such as oxygen-containing groups on rGO surface and the step edges in rGO boundaries. To our best knowledge, it is the first time to report that in situ ZnO/rGO nanohybrids perform self-powered and fast (the response time of 0.1 s and the recovery time of 0.2 s) photoresponse to ultraviolet light. The fast and self-powered photocurrent generation can be attributed to the Schottky contact at the rGO/ZnO interface. These results demonstrate an effective way to promote the wide applications in light energy harvesting devices based on semiconductor/graphene hybrids including solar cells, photodetectors, sensors and photocatalysis.

Interfacial Layer Control by Dry Cleaning Technology for Polycrystalline and Single Crystalline Silicon Growth.

Native oxide removal prior to poly-Si contact and epitaxial growth of Si is the most critical technology to ensure process and device performances of poly-Si plugs and selective epitaxial growth (SEG) layers for DRAM, flash memory, and logic device. Recently, dry cleaning process for interfacial oxide removal has attracted a world-wide attention due to its superior passivation properties to conventional wet cleaning processes. In this study, we investigated the surface states of Si substrate during and after dry cleaning process, and the role of atomic elements including fluorine and hydrogen on the properties of subsequent deposited silicon layer using SIMS, XPS, and TEM analysis. The controlling of residual fluorine on the Si surface after dry cleaning is a key factor for clean interface. The mechanism of native oxide re-growth caused by residual fluorine after dry cleaning is proposed based on analytical results.