Control Of Semiconductor Manufacturing Processes Research Articles

Multi-Domain Data Integration for Plasma Diagnostics in Semiconductor Manufacturing Using Tri-CycleGAN

The precise monitoring of chemical reactions in plasma-based processes is crucial for advanced semiconductor manufacturing. This study integrates three diagnostic techniques—Optical Emission Spectroscopy (OES), Quadrupole Mass Spectrometry (QMS), and Time-of-Flight Mass Spectrometry (ToF-MS)—into a reactive ion etcher (RIE) system to analyze CF4-based plasma. To synchronize and integrate data from these different domains, we developed a Tri-CycleGAN model that utilizes three interconnected CycleGANs for bi-directional data transformation between OES, QMS, and ToF-MS. This configuration enables accurate mapping of data across domains, effectively compensating for the blind spots of individual diagnostic techniques. The model incorporates self-attention mechanisms to address temporal misalignments and a direct loss function to preserve fine-grained features, further enhancing data accuracy. Experimental results show that the Tri-CycleGAN model achieves high consistency in reconstructing plasma measurement data under various conditions. The model’s ability to fuse multi-domain diagnostic data offers a robust solution for plasma monitoring, potentially improving precision, yield, and process control in semiconductor manufacturing. This work lays a foundation for future applications of machine learning-based diagnostic integration in complex plasma environments.

Neural network driven sensitivity analysis of diffraction-based overlay metrology performance to target defect features

Overlay (OVL) is one significant performance indicator for the lithography process control in semiconductor manufacturing. The accuracy of the OVL metrology is extremely critical for guarantee the lithography quality. Currently, diffraction-based overlay (DBO) is one of the mainstream OVL metrology techniques. Unfortunately, the accuracy of the DBO metrology is largely affected by the defect features of the OVL target. Therefore, there is a strong need to investigate the impacts of these target defects on the DBO metrology performance. However, efficiently investigating the statistical and interactive impacts of various DBO target defects remains challenging. This study aims to address this issue through proposing an intelligent sensitivity analysis approach. A cumulative distribution based global sensitivity analysis (GSA) method is utilized to assess the nonlinear influences of multiple defects in the OVL target on the DBO inaccuracy. The scenarios with both known and unknown distributions of the OVL target defects are considered. For the former, a neural network driven forward model is constructed for fast calculating the optical diffraction responses to accelerate the GSA process. For the latter, another neural network based inverse model are built for efficiently estimating the distribution of the target defects. Finally, a series of simulation experiments are conduct for typical DBO targets with multiple common defect features. The results demonstrate the effectiveness and robustness of the proposed approach as well as give valuable insights into the DBO defect analysis. Our study provides a strong tool to assist the practitioners in achieving intelligent and efficient DBO analysis and thus in enhancing OVL metrology performance.

Deep Learning-based Sequence Modeling for Advanced Process Control in Semiconductor Manufacturing

Semiconductor manufacturing is one of the most data-intensive industries in manufacturing. Many so-called Advanced Process Control (APC) approaches based on equipment or process data have been presented over the years to improve quality and efficiency, reduce waste and increase energy savings. While on the one hand, intensive production leads to large amount of data available for the development of Machine Learning-based technologies, on the other hand, the high-mix production, multiple processes and machines lead researchers and developers to deal with ’small data’ scenarios. In this context, domain adaptation approaches are highly relevant to enhance scalability. In this work, we are extending a state-of-the-art Deep Learning architecture called Domain Adversarial Neural Network based Alignment Model (DBAM) by considering new sequence learning layers. In the real-world case study, the proposed architecture is shown to achieve higher accuracy, allow for better management in the absence of large amounts of data and make previously trained models reusable in similar scenarios.

Joint Feature and Label Adversarial Network for Wafer Map Defect Recognition

Deep neural networks (DNNs), e.g., convolutional neural network (CNN), are able to learn effective features from wafer maps for dimensional reduction and feature extraction. However, very large image data are needed to train DNNs to obtain high generalization performance. It is still a difficult task due to the lack of sufficient labeled images with various defects. This article proposes a semisupervised deep transfer learning algorithm called joint feature and label adversarial network (JFLAN). JFLAN uses CNNs to extract transferable features of wafer maps and then introduces a multilayer domain adaptation and pseudolabel learning block based on the generative adversarial network (GAN). This effectively reduces the distribution discrepancy and the among-class distance of the transferable features. Finally, JFLAN transfers knowledge from wafer image source data collected offline and then achieves the goal of significantly improved accuracy of wafer defect recognition and realizes online adaptive defect recognition. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Note to Practitioners</i> —The defect recognition on wafer maps plays a key role to recognize fault sources of the semiconductor manufacturing processes. Transfer learning is able to use the existing labeled data to assist in the classification of unlabeled data and is very effective to solve the problem of small samples and nonstationary generalization errors. In particular, the infusion of adversarial learning in transfer learning will provide a new idea for deep feature learning. This article provides a novel method based on transfer learning to implement wafer map defect recognition (WMDR) to quickly identify defect root causes for yield enhancement. This article provides a novel way for quality control of semiconductor manufacturing processes based on transfer and adversarial learning.

Temperature Compensation by Embedded Temperature Variation Method for an AC Voltammeric Analyzer of Electroplating Baths

AbstractAn in‐situ sensor utilizing a variety of DC‐ and AC‐voltammetric techniques is an integral component of the on‐line monitoring system that provides a complete chemical analysis of different plating solutions by predicting concentration values of all deliberately‐added bath constituents with a single device despite differences in the constituents’ chemical properties. Such sensors are employed routinely for electroplating process control in semiconductor manufacturing. This voltammetric approach exploits quantitatively the physicochemical processes (like adsorption) which are temperature dependent. Therefore the accuracy of analyte concentration predictions can be affected adversely by temperature fluctuations. This paper introduces a novel comprehensive method which allows the mitigation of temperature variation effects on voltammetric scans allowing accurate concentration prediction. Specifically, this study introduces a multi‐step rigorous routine for the development and subsequent validation of the analytical method utilizing a chemometric model with temperature variation embedded in regression for exemplary determination of leveler additive concentration. This approach analyses the effect on AC voltammograms resulting from two qualitatively indistinguishable sources of variation: leveler concentration and temperature. A critical step of this routine of fundamental novelty, which aims to select the variables (index points of voltammogram) to be utilized for building of the analytical model in the presence of two concurrent sources of variation, is introduced to incorporate temperature variation.

Sounding out buried nanostructures using subsurface ultrasonic resonance force microscopy

ABSTRACTImaging of nanoscale structures buried in a covering material is an extremely challenging task, but is also considered extremely important in a wide variety of fields. From fundamental research into the way living cells are built up to process control in semiconductor manufacturing would all benefit from the capability to image nanoscale structures through arbitrary covering layers. Combining Atomic Force Microscopy (AFM) with ultrasound has been shown a promising technology to enable such imaging in various configurations. Here we report the development of an alternative method of combining AFM with ultrasound which we call SubSurface Ultrasonic Resonance Force Microscopy (SSURFM) and which is based on a combination of the two most common variants described in literature, which each have their specific strong points: Ultrasonic Force Microscopy (UFM) and Contact Resonance AFM (CR-AFM). We show the excellent performance of this combination on a number of samples designed specifically to mimic relevant conditions for the application as a metrology technique in the semiconductor manufacturing process. We also discuss the physics of the image contrast mechanism which is based on sensing local changes in visco-elastic properties of the sample bygenerating large indentations in the surface.

Temperature Compensation by Calibration Transfer for an AC Voltammetric Analyzer of Electroplating Baths

AbstractThe application of methods for mitigating the effects of temperature fluctuations on the analytical performance of an in‐situ DC‐ and AC‐voltammetric sensor employed for electroplating process control in semiconductor manufacturing is presented. This sensor is a part of an automated analytical system capable of predicting concentration values of deliberately‐added bath constituents based on the component‐specific multivariate voltammetric responses. However, these responses include physicochemical phenomena, some of which are strongly dependent on temperature; therefore temperature fluctuations can produce an additional source of variance in the voltammetric responses adversely affecting the accuracy of analyte concentration predictions. Several calibration‐transfer‐based techniques, both discrete and continuous, using Piecewise Direct Standardization and Direct Standardization combined with PCR and PLS analytical models are comparatively validated for temperature compensation using AC voltammetric data for the example of accelerator additive. An extension of implementation of continuous methods for Direct Standardization is proposed along with an introduction of a new hybrid method of Standardization Models.

A Kalman filter-based R2R control system with parallel stochastic disturbance models for semiconductor manufacturing processes

A Kalman filter-based run-to-run control system has been proposed for minimum variance control of semiconductor manufacturing process. In the proposed control system, both gain- and bias-varying process models combined with different stochastic disturbance models were considered and identified in parallel. The best-fit model is selected and used for the R2R controller design. Sub-models of the ARIMA(1,1,1) process were considered for stochastic modeling of the bias and gain variation, and the Kalman filters are used to find the optimum model parameter estimation. The control performance was analyzed for each case of the disturbance model to investigate the expected benefit from the control system in comparison with the EWMA filter-based controller.

Integration of scheduling and advanced process control in semiconductor manufacturing: review and outlook

Scheduling in semiconductor manufacturing is of vital importance due to the impact on production performance indicators such as equipment utilization, cycle time, and delivery times. With the increasing complexity of semiconductor manufacturing, ever-new products and demanding customers, scheduling plans for efficient production control become crucial. Scheduling and control are mutually dependent as control requires information from scheduling, for example, where jobs are processed, and scheduling requires control information, for example, on which equipment operations can be processed. Based on a survey of the literature, this article proposes a review and an outlook for the potential improvements by binding scheduling decisions and information coming from advanced process control systems in semiconductor manufacturing.

An Adaptive Bayesian Method for Semiconductor Manufacturing Process Control With Small Experimental Data Sets

In capital intensive semiconductor manufacturing processes it is often impractical to run large designed experiments and the amount of experimental data available is often not adequate to build sufficiently accurate statistical models or reliably estimating optimal conditions. This paper presents a new Bayesian predictive approach, referred to as the Bayesian adaptive design of experiments, for sequential design of experiments that aims to combine experimentation and optimization stages in order to start production more quickly with a small amount of process data. A dual control approach that simultaneously considers model estimation and optimization objectives is adopted and an adaptive Bayesian response surface model is used. It is shown that the optimal solution of the experimental settings can be determined either numerically for the case of a general second-order model or in analytical closed-form for the case of a first-order model. The effectiveness of the approach is illustrated with a simulation example and a real semiconductor process data taken from the literature. It is shown that by employing the proposed adaptive Bayesian approach one can simultaneously learn the process while not requiring excessive perturbations away from the target level and can achieve faster model estimation than central composite experimental designs. The learning weight used in the dual cost function allows one to tune the relative weights of learning and control goals depending on the uncertainty about the process model.

Analysis of Interaction Structure Among Multiple Functional Process Variables for Process Control in Semiconductor Manufacturing

Our previous work has shown that complex interaction patterns among functional process variables (FPVs) in semiconductor manufacturing processes can indicate process condition changes. We developed a nonlinear dynamics model to describe interactions among FPVs, which was further used to monitor process condition changes. However, the interaction structure among three or more FPVs has not been thoroughly investigated for the purpose of process control. In this work, we first extend our previously developed nonlinear dynamics model by considering the autocorrelation in each FPV. A generalized least square (GLS) method is applied to estimate the extended model. The interaction structure among FPVs is represented as a complex network in which the directionality and strength of interaction are discovered from the extended nonlinear dynamics model. To validate the proposed method, we first conduct simulation study using van del Pol oscillators. Then two sets of real experimental data from chemical mechanical planarization process are used to investigate the interaction structure change over a polishing cycle. The results show that the extracted patterns of interaction structure among FPVs aid to uncover the polishing mechanisms and provide more insights for condition monitoring and diagnosis.

Advanced 3D-AFM Metrology for Sidewall Spacers

Gate spacer engineering has become one of the primary concerns in dimensional metrology for semiconductor manufacturing process control. In composite spacers, deposition and etch of each spacer determine where the transistor source/drain implants occur. The sidewall spacer thickness and profile, especially at the feature bottom, is critical to be characterized and controlled by applicable 3D metrology. This paper discusses recent advances in 3D atomic force microscopy (3D-AFM) that solve the specialized characterization needs for critical sidewall spacer geometry controls, including multiple spacer thickness and nitride spacer pulldown. 3D-AFM metrology measures with greater accuracy such typical gate spacer parameters as linewidth, height, pitch, sidewall profile, sidewall angle (SWA), line edge roughness (LER), and line width variation (LWV), and sidewall roughness (SWR).

Friction modeling in linear chemical-mechanical planarization

In this article, we develop an analytical model of the relationship between the wafer/pad friction and process configuration. We also provide experimental validation of this model for in situ process monitoring. CMP thus demonstrates that the knowledge and methodologies developed for friction modeling and control can be used to advance the understanding, monitoring, and control of semiconductor manufacturing processes. Meanwhile, relevant issues and challenges in real-time monitoring of CMP are presented as sources of future development.

On-line tuning system of multivariate dEWMA control based on a neural network approach

The double exponentially weighted moving average (EWMA) controller is a popular algorithm for on-line quality control of semiconductor manufacturing processes. The performance of the closed-loop system hinges on the adequacy of the two weight parameters of the double EWMA equations. In 2004, Su and Hsu presented an approach based on the neural technique for ‘on-line’ tuning the weight of the single EWMA equation in the single-input single-output (SISO) system. The present paper extends the neural network on-line tuning scheme to the double EWMA controller for the non-squared multiple-input multiple-output (MIMO) system, and validates the control performance by means of a simulated chemical–mechanical planarization (CMP) process in semiconductor manufacturing. Both linear and non-linear equipment models are considered to evaluate the proposed controller, coupling with the deterministic drift, the Gaussian noise and the first-order integrated moving average (IMA) disturbance. It has been shown from a variety of simulation studies that the proposed method exhibits quite competitive control performance as compared with the previous control system. The other merit of the proposed approach is that the tuning system, if sufficient training in a neural network is available, can be practicably applied to complex semiconductor processes without undue difficulty.

Virtual metrology and feedback control for semiconductor manufacturing processes using recursive partial least squares

Virtual metrology (VM) is the prediction of metrology variables (either measurable or non-measurable) using process state and product information. In the past few years VM has been proposed as a method to augment existing metrology and has the potential to be used in control schemes for improved process control in terms of both accuracy and speed. In this paper, we propose a VM based approach for process control of semiconductor manufacturing processes on a wafer-to-wafer (W2W) basis. VM is realized by utilizing the pre-process metrology data and more importantly the process data from the underlying tools that is generally collected in real-time for fault detection (FD) purposes. The approach is developed for a multi-input multi-output (MIMO) process that may experience metrology delays, consistent process drifts, and sudden shifts in process drifts. The partial least squares (PLS) modeling technique is applied in a novel way to derive a linear regression model for the underlying process, suitable for VM purposes. A recursive moving-window approach is developed to update the VM module whenever metrology data is available. The VM data is then utilized to develop a W2W process control capability using a common run-to-run control technique. The proposed approach is applied to a simulated MIMO process and the results show considerable improvement in wafer quality as compared to other control solutions that only use lot-to-lot metrology information.

A Bayesian Approach for Disturbance Detection and Classification and Its Application to State Estimation in Run-to-Run Control

With growing demand for effective management of abnormal situations in process industry, disturbance detection and classification has drawn considerable interest from researchers in both industry and academia. In this paper, a disturbance detection and classification method is developed using Bayesian statistics. The theoretical derivation of the proposed method as well as its practical implementation are provided. With the introduction of preand post-change windows, detection and classification are achieved simultaneously in the proposed method through matching the posterior probability pattern to predefined patterns. An overlapping window mechanism is incorporated into the proposed method to minimize detection and classification delay. A simulation example is given to illustrate the robustness and effectiveness of the proposed disturbance detection method. One application of the proposed Bayesian disturbance detection and classification algorithm is a Bayesian enhanced exponentially weighted moving average (B-EWMA) state estimator which improves state estimation in the run-to-run control of semiconductor manufacturing processes. The superior performance of B-EWMA compared to the conventional EWMA is demonstrated using an industrial example

Statistical process adjustment: a brief retrospective, current status, and some opportunities for further work

Industrial statisticians frequently face problems in their practice where adjustment of a manufacturing process is necessary. In this paper, a view of the origins and recent work in the area of statistical process adjustment (SPA) is provided. A discussion of some topics open for further research is also given including new problems in semiconductor manufacturing process control. The goal of the paper is to help display the SPA field as a research area with its own identity and content, and promote further interest in its development and application in the industry.

Semiconductor manufacturing process control and monitoring: A fab-wide framework

The semiconductor industry has started the technology transition from 200 mm to 300 mm wafers to improve manufacturing efficiency and reduce manufacturing cost. These technological changes present a unique opportunity to optimally design the process control systems for the next generation fabs. In this paper we first propose a hierarchical fab-wide control framework with the integration of 300 mm equipment and metrology tools and highly automated material handling system. Relevant existing run-to-run technology is reviewed and analyzed in the fab-wide control context. Process and metrology data monitoring are discussed with an example. Missing components are pointed out as opportunities for future research and development. Concluding remarks are given at the end of the paper.

Diffuse x-ray streaks from stacking faults in Si analyzed by atomistic simulations

Since extrinsic stacking faults can form during postimplantation annealing of Si, understanding their properties is important for reliable control of semiconductor manufacturing processes. We demonstrate how grazing incidence x-ray scattering methods can be used as a nondestructive means for detecting extrinsic stacking faults in Si. Atomistic analysis of diffuse intensity streaks is used to determine the size of the faults, the minimum size at which the streak pattern in the scattering will be visible, and the magnitude of atomic displacements in the center of the stacking fault.

Monitoring and control of semiconductor manufacturing processes

Concerns optical measurement techniques for semiconductor manufacturing process monitoring and control. They can provide previously impossible real-time monitoring of several process variables, in-situ or ex-situ. This further enables the applications of more sophisticated real-time control algorithms, other than SPC. The SPC-based run-to-run (RtR) control, on the other hand, is still an instrumental part of the control algorithm, whenever there is a lack of real-time sensors for measuring critical process metrics. An emerging practice is to integrate RtR with the real-time control design to provide a comprehensive control design algorithm for semiconductor manufacture. The continued trend of semiconductor industry is toward an bigger wafers and smaller devices. This requires more integrated supervisory control, able to provide even tighter control, especially for photolithography, CVD, and etch processes. A unified framework needs to be established, at least for these critical processes, to facilitate and expedite systematic control design and development. In addition, as more sophisticated algorithms are being implemented, the control-related software and hardware should be user-friendly so that it can be operated by nonexpert personnel. Finally, since chip manufacturing consists of various processes, a comprehensive control algorithm on a factory-wide basis should utilize information (process-state, wafer-state, and tool-state data) from the current process as well as upstream and downstream processes.