Problem Of Test Pattern Generation Research Articles

A novel two-fold state skip logic Built-In Self-Test scheme for digital circuits

Recent developments in the field of very-large-scale integration (VLSI) testing have led to a demand for fault diagnosis in very-large-scale integration circuits. However, the problem of test pattern generation becomes very difficult as the size of circuits increases. Proficient techniques for test pattern generation are necessary to reduce the test sequence length and testing time. In conventional methods, Automatic Test Pattern Generation (ATPG) and Design for Test (DFT) are used for test pattern generation and fault insertion in netlist files. The complexity faced in Automatic Test Pattern Generation exponentially increases with respect to the circuit size. In circuits with a large number of stuck-at-fault errors, the conventional verification sequence fails to provide acceptable fault coverage and low power consumption. A twofold state skip (TFSS) logic is developed to achieve a low scan power by skipping long scan chains to reduce switching activities. This work addresses the above-mentioned issues faced in Automatic Test Pattern Generation in VLSI circuits and examines all detectable faults using a twofold state skip logic. The proposed approach is efficient and verified on ISCAS 89 & 85 benchmark circuits; the results indicate a considerable reduction in the test data volume and thus a significant reduction in power consumption.

Soft Computing Approach To Automatic Test Pattern Generation For Sequential Vlsi Circuit

Due to the constant development in the integrated circuits, the automatic test pattern generation problem become more vital for sequential vlsi circuits in these days. Also testing of integrating circuits and systems has become a difficult problem. In this paper we have discussed the problem of the automatic test sequence generation using particle swarm optimization(PSO) and technique for structure optimization of a deterministic test pattern generator using genetic algorithm(GA).

An exact solution to the minimum size test pattern problem

This article addresses the problem of test pattern generation for single stuck-at faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of "don't care" conditions to be used in the synthesis of Built-In Self-Test (BIST) logic. The proposed solution is based on an integer linear programming (ILP) formulation which builds on an existing Propositional Satisfiability (SAT) model for test pattern generation. The resulting ILP formulation is linear on the size of the original SAT model for test generation, which is linear on the size of the circuit. Nevertheless, the resulting ILP instances represent complex optimization problems, that require dedicated ILP algorithms. Preliminary results on benchmark circuits validate the practical applicability of the test pattern minimization model and associated ILP algorithm.

Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams

In this paper, we present an algorithm for generating test patterns automatically from functional register-transfer level (RTL) circuits that target detection of stuck-at faults in the circuit at the logic level. In order to do this, we utilize a data structure named assignment decision diagram that has been proposed previously in the field of high-level synthesis. With the advent of RTL synthesis tools, functional RTL designs are now widely used in the industry to cut design turn around time. This paper addresses the problem of test pattern generation directly at this level due to a number of advantages inherent at the RTL. Since the number of primitive elements at the RTL is usually less than the logic level, the problem size is reduced leading to a reduction in the test-generation time over logic-level automatic test pattern generation (ATPG). Also, a reduction in the number of backtracks can lead to improved fault coverage and reduced test application time over logic-level techniques. The test patterns thus generated can also be used to perform RTL-RTL and RTL-logic validation. The algorithm is very versatile and can tackle almost any type of single-clock design, although performance varies according to the design style. It gracefully degrades to an inefficient logic-level ATPG algorithm if it is applied to a logic-level circuit. Experimental results demonstrate that over 1000 times reduction in test-generation time can be achieved by this algorithm on certain types of RTL circuits without any compromise in fault coverage.

Partial-scan delay fault testing of asynchronous circuits

Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. Previous work has shown that full-scan delay-fault testing of asynchronous circuits is feasible. In this work, we tackle the problem of partial-scan testing, which requires test-pattern generation on a sequential circuit. We show how this problem can be effectively reduced to a classical problem of stuck-at test-pattern generation for a related combinational circuit. The reduction is done in three steps. The first step reduces testing of an asynchronous sequential circuit, by using a partial-scan approach, to testing an object called an asynchronous net, in which feedback is allowed only inside asynchronous memory elements. We then decompose the problem of testing asynchronous nets into that of initializing memory elements (the second step), followed by robust path delay fault testing (the third step). We provide effective procedures to solve both the initialization and the test-pattern generation problem. The technique is complete, automated, and requires only partial scan of some memory element outputs.

Algebraic test-pattern generation based on the Reed–Muller spectrum

In the last few years new test generation procedures based on Boolean techniques have been reported. Despite the fact that Boolean operations are in general computationally expensive and that procedures are available based on path-oriented methods of reasonable efficiency, there is still interest in developing new methods to speed up the detection of those faults that are hard to detect by the path-oriented methods, to reduce the test lengths obtained, or to make it possible to use parallel machines more efficiently. A new algebraic procedure to determine test patterns for stuck-line faults in combinational logic circuits is proposed. It is based on the use of Reed–Muller coefficients to build and solve the equation that describes the Boolean difference between the circuit affected by a given fault and the correct one. It is also shown how digital spectral techniques, which have been widely used in the synthesis of switching functions and in the determination of circuit signatures for built-in self testing, can also be applied to the test-pattern generation problem. The procedure has proved its efficiency when applied to the standard ISCAS benchmark circuits.

A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits

In this paper, we present a circuit partitioning and test pattern generation technique for pseudo-exhaustive built-in self-testing of VLSI circuits. The circuit partitioning process divides a given circuit into a set of subcircuits which can be exhaustively tested, while the test pattern generation process generates reduced exhaustive test patterns for each subcircuit using a linear feedback shift register (LFSR). In conventional approaches, these two problems are considered separately. However, in this paper, both problems are considered and solved in the same phase. A graph theoretic model of VLSI circuits is proposed. Based on this model, a circuit partitioning algorithm using the concept of minimum vertex cut is devised to partition the circuit into a set of exhaustively testable subcircuits with restricted hardware overhead. Each time a subcircuit is generated by the partitioning algorithm, the test pattern generation problem is considered. A new algorithm, based on the subcircuit modification technique, is proposed with the objective of generating reduced exhaustive test patterns of limited length (e.g., /spl les/2/sup 20/) using LFSR's, for each of the subcircuits. This task is embedded in the circuit partitioning process itself, leading to an efficient and well-coordinated solution. Experiments using ISCAS benchmark circuit simulation have been conducted. The results demonstrate that the proposed method is very good. >

Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization

Motivated by the problem of test pattern generation in digital circuits, this paper presents a novel technique called recursive learning that is able to perform a logic analysis on digital circuits. By recursively calling certain learning functions, it is possible to extract all logic dependencies between signals in a circuit and to perform precise implications for a given set of value assignments. This is of fundamental importance because it represents a new solution to the Boolean satisfiability problem. Thus, what we present is a new and uniform conceptual framework for a wide range of CAD problems including, but not limited to, test pattern generation, design verification, as well as logic optimization problems. Previous test generators for combinational and sequential circuits use a decision tree to systematically explore the search space when trying to generate a test vector. Recursive learning represents an attractive alternative. Using recursive learning with sufficient depth of recursion during the test generation process guarantees that implications are performed precisely; i.e., all necessary assignments for fault detection are identified at every stage of the algorithm so that no backtracks can occur. Consequently, no decision tree is needed to guarantee the completeness of the test generation algorithm. Recursive learning is not restricted to a particular logic alphabet and can be combined with most test generators for combinational and sequential circuits. Experimental results that demonstrate the efficiency of recursive learning are compared with the conventional branch-and-bound technique for test generation in combinational circuits. In particular, redundancy identification by recursive learning is demonstrated to be much more efficient than by previously reported techniques. In an important recent development, recursive learning has been shown to provide significant progress in design verification problems. Also importantly, recursive learning-based techniques have already been shown to be useful for logic optimization. Specifically, techniques based on recursive learning have already yielded better optimized circuits than the well known MIS-II.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Computations over finite monoids and their test complexity

We consider the test pattern generation problem for circuits, which compute expressions over some algebraic structure. The relation between algebraic properties of this structure and test complexity (i.e. the best possible test size) is analyzed. Here, this relation is looked at in detail for the family of all finite monoids. The test complexity of a monoid with respect to a problem is measured by the number of tests needed to check the best testable circuit (in a certain computational model) solving the problem. Two important computations over finite monoids namely expression evaluation and parallel prefix computation are considered. The relation between algebraic properties of a monoid and its test complexity (with respect to these problems) is studied. In both cases it can be shown that the set of all finite monoids partitions into exactly three classes with constant, logarithmic and linear test complexity, respectively. These classes are characterized using algebraic properties. For example groups are exactly the monoids with constant test complexity. For each class we provide circuits with optimal test sets and efficient methods, which decide the membership problem for a given finite monoid M, i.e. determine the test complexity for M.

Test Pattern Generation for API Faults in RAM

In this correspondence we consider the problem of test pattern generation for random-access memory to detect pattern-sensitive faults. A test algorithm is presented which contains a near-optimal WRITE sequence and is an improvement over existing algorithms. The algorithm is well suited for built-in testing applications.