Floorplanning Problem Research Articles

Non-Slicing Very Large Scale Integration Floorplan Optimization Technique Using an Improved Modified Memetic Algorithm with O-Tree Representation

Interconnects in the VLSI floorplan play an essential role in determining a particular chip’s speed and parametric losses. For researchers, balancing between optimization of area and wirelength has been the central focus. This paper has proposed an improved memetic algorithm according to the floorplan problem in which the Genetic Algorithm is used for global exploration and an inherent efficient local search method for improving the result in the search region. The representation used for the floorplan is O-Tree (Ordered Tree) implemented through the Code-Based Location Search and Position (CBLSP) methodology. For wirelength calculation, the Half Perimeter Wire Length (HPWL) methodology is utilized. The mentioned techniques are checked on MCNC benchmark circuits with different preferences for wirelength and area. It has been found that the proposed methodology has generated the best and near to best results for area. In terms of wirelength, the proposed methodology has shown improvement with a range of 3.97%–65.47%. For multi-objective optimization with the area and wirelength (α = 0.5, β = 0.5), significant improvement in wirelength with a 25.1% decrease for the APTE benchmark, 47.4% decrease for HP Benchmark, and 10.7% decrease for the AMI33 benchmark circuit has been recorded.

A Quasi-Newton-based Floorplanner for fixed-outline floorplanning

We address the problem of floorplanning, a crucial step of VLSI design, and propose a novel approach named Quasi-Newton-based FloorplannER (QinFer) for the challenging fixed-outline floorplanning problem. QinFer is an effective two-phase method. The first phase recursively bipartitions the original circuit to a set of subcircuits until each leaf subcircuit contains only one module. By placing each module onto the suboutline of the leaf subcircuit, a distributed floorplan is obtained. The recursive bipartition enables the strongly connected modules to be placed closely so that the obtained floorplan has a good quality of wirelength. By bipartitioning the circuit into leaf subcircuits with only one module and using terminal propagation technology during the whole bipartitioning process, the capabilities of bipartition tool and terminal propagation technology in improving quality of wirelength are fully utilized. The second phase contributes a potential energy function to evaluate the overlap among the modules as well as the protruding portion of modules beyond the outline, and a Quasi-Newton method is employed to reduce the potential energy for the legalization of the distributed floorplan. The Quasi-Newton legalization method is a general method that can be used to calculate a floorplan without constructing any geometric representations for the modules. Moreover, the robustness of QinFer is further improved by incorporating a refined distribution algorithm to establish feasibility for the case of illegal floorplan. Extensive experimental results on public benchmarks show that, in comparison to the well-known approaches DeFer and F-FM, QinFer can generate 7.3% and 2.1% better half-perimeter wirelengths, respectively.

An Adaptive Symbiosis based Metaheuristics for Combinatorial Optimization in VLSI

The elevated perplexity in solving non deterministic problems (NP-Hard) has opened the way for the emergence of several metaheuristics. Most of the real time problems pertaining to electronics are Multi-Objective Optimization Problem (MOOP). Hence, there is always a conflict between several tradeoffs. While delving in to past anthologies, it is evident that biologically inspired algorithm tend to solve NP-Hard problems in a more appreciable manner since nature optimizes at the best. This research work contemplates the problem of VLSI floorplanning and solves the mentioned problem with a symbiosis based metaheuristics. Symbiosis is a natural phenomenon wherein organisms interact amongst themselves for survival. A usual symbiosis has three phenomenon packed: Mutualism phase, Commensalism phase and parasitism phase. However, in the adaptive mechanism there is a deciding factor which decides which phase has to commence. The problem was tested with MCNC benchmarks and has yielded palpable results over few other algorithms under test. With the proposed algorithm, in the problem of VLSI floorplanning, wirelength and area were considered as the objectives that were optimized which eventually resulted in the minimization of dead space (unused space) in the circuit

Performance evaluation of heuristic algorithms in floor planning for ASIC design

A study on physical design of VLSI Floor planning is discussed using optimization techniques for betterment in performance of VLSI chip. Floor planning in VLSI is considered to be a Non Polynomial problem. Such problems can be solved using computations. The initial step in floor plan is the representation of floor plan design. The floor plan representations show greater impact on the search space and the complexity of the floor plan design. The objective of this paper is to study different algorithms that addressees the problem of handling alignment constraints such as good placement, optimum area and short run time. Different heuristic and meta-heuristic algorithms are proposed and suggested by many researchers for solving the VLSI Floor plan problem. In this paper Simulated Annealing algorithm, Ant Colony Algorithm, Tabu search and Genetic algorithms are discussed.

A Novel High Speed Simulated Annealing Algorithm for Non-Slicing VLSI Floorplanning using B*-Tree Representation

Objective: To optimise area, interconnecting wirelength and dead space of very large scale integration non-slicing floorplan with high computation speed using evolutionary algorithm intelligently. Methods/Statistical Analysis: Floorplanning is one of the most important steps in physical design automation in very large scale integration (VLSI) and to solve the problem of VLSI floorplanning is an art. Parameters like chip performance, sizing of modules in a chip, yield and reliability of chip are determined using VLSI floorplanning. The Simulated algorithm and B*-tree structure have been implemented in C++ language and compiled in GCC compiler of Ubuntu14.04. Findings: Parameters like chip performance, sizing of modules in a chip, yield and reliability of chip are determined using VLSI floorplanning. Many computer-aided design algorithms are developed for the NP-hard problems like VLSI floorplanning. A simulated annealing (SA) algorithm for the hard module and non-slicing VLSI floorplanning problem is presented. The SA uses a new acquisitive method to construct an initial B*-tree and a new process to explore the search space. Application/Improvements: The SA has been implemented and experimental result with optimisation of area, dead space, wirelength and best timing constraints have been tested on Microelectronic Center of North Carolina (MCNC) benchmarks.

A Novel Approach for System-On-Chip Test Scheduling using Genetic Algorithm

In this paper, an efficient approach for the test scheduling problem of core based systems based on a two-stage Genetic Algorithm has been presented. The System-On-Chip [SOC] test scheduling problem is formulated in to a floor plan problem and sequence pair is used to represent it, meanwhile, a two-stage Genetic Algorithm is used to search for desired solutions. This two-stage Genetic Algorithm based method was implemented in C programming language and applied to ITC’02 SOC test benchmark. Experimental results show that lower testing time was obtained by this method compared to the other methods.

Multi-bend bus-driven floorplanning considering fixed-outline constraints

The rapid rate of technological advances makes it necessary for very large scale integration (VLSI) floorplanning to consider not only interconnect constraints, but also fixed-outline constraints. In this paper, we propose a new approach to address the problem of Bus-Driven Floorplanning (BDF) within a fixed die. By providing the width and height of a chip, a set of circuit blocks and the bus specifications (i.e., the width of each bus and the blocks that the bus needs to go through), the approach will generate a final floorplan that satisfies the following requirements: (a) all blocks are packed within the fixed outline, (b) all buses are routable and (c) the floorplan area and total bus area are minimized. Based on the deterministic algorithm Less Flexibility First (LFF), our approach does not need to resort to a floorplan representation and functions very well in fixed-outline floorplanning. Our approach places no limitations on the shape of the buses, and the processes of block packing and bus packing proceed simultaneously. According to the experimental results, our approach can generate a good solution with a lower percentage of dead space, a shorter total length of all buses and a shorter run time, even under fixed-outline constraints. In addition, our algorithm works well for large and complex test cases that have not been studied in previous research.

SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems

In this paper, we propose an SKB-tree representation for two modern floorplaning problems: fixed-outline and voltage-island driven floorplanning. Since SKB-tree can dynamically allocate regions for blocks so that all blocks can be placed into a specific outline for each solution, it is a suitable representation for dealing with the fixed-outline constraint. Due to this good property, we also use it to deal with the voltage-island driven floorplanning. Different from previous works, we constrain blocks of the same voltage to be placed into one region to save power routing resource, simplify power planning, and reduce IR Drop. Experimental results show the feasibility of SKB-tree. For the fixed-outline constraint with zero deadspace, SKB-tree achieved significantly better wirelength than A-FP, Parquet 4.0, ZDS, and SAFFOA. SKB-tree can get better results than other fixed-outline driven floorplanners because it only needs to focus on wirelength optimization during simulated annealing. Besides, for voltage island driven floorplanning, SKB-tree also consumes less power and wirelength.

DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm

In this paper, we present DeFer-a fast, high-quality, scalable, and nonstochastic fixed-outline floorplanning algorithm. <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DeFer</i> generates a nonslicing floorplan by compacting a slicing floorplan. To find a good slicing floorplan, instead of searching through numerous slicing trees by simulated annealing as in traditional approaches, DeFer considers only one single slicing tree. However, we generalize the notion of slicing tree based on the principle of deferred decision making (DDM). When two subfloorplans are combined at each node of the generalized slicing tree <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">,</i> DeFer does not specify their orientations, the left-right/top-bottom order between them, and the slice line direction. DeFer even does not specify the slicing tree structure for small subfloorplan. In other words, we are deferring the decisions on these factors, which are specified arbitrarily at an early step in traditional approaches. Because of DDM, one slicing tree actually corresponds to a large number of slicing floorplan solutions, all of which are efficiently maintained in one single shape curve. With the final shape curve, it is straightforward to choose a good floorplan fitting into the fixed outline. Several techniques are also proposed to further optimize the wirelength. For both fixed-outline and classical floorplanning problems, experimental results show that DeFer achieves the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">best</i> success rate, the best wirelength, the best runtime, and the best area on average compared with all other state-of-the-art floorplanners.

Temperature-aware floorplanning via geometric programming

With microprocessor power densities escalating rapidly when technology scales below nanometer regime, there is an exigent need for developing innovative cooling systems for electronic product design. The high temperature of chips greatly affects its reliability, raises the leakage power consumed to unprecedented levels, and makes cooling systems significantly more expensive. The maximum temperature of a block in a chip depends not only on its own power density, but also on the chip area in each blocks. In this paper, we employ geometric programming (GP) for the optimization problem of temperature reduction and chip area floorplanning. We notice that the formulated model is a nonlinear convex problem; consequently, its solution can be solved GP method. Based upon an incremental floorplanning problem together with the GP model, the temperature-aware floorplanning scheme significantly reduces peak module temperature with minimal chip area impact. For Microelectronics Center of North Carolina (MCNC) ami33 under a testing environment temperature of 0 ∘C, compared with the maximum temperature of the original module, the maximum temperature of the optimized one could be reduced from 90 ∘C to 10 ∘C, where the minimized chip area is about 700 mm 2. For the case of MCNC ami49, the maximum temperature reduction is 60 ∘C (i.e., its reduction is from 65 ∘C to 5 ∘C) with a minimal chip area of 2500 mm 2. We have numerically found a floorplan which can reduce the maximum temperature of the chip and minimize the chip area while maintaining comparable performance simultaneously.

Multi-bend bus driven floorplanning

In this paper, the problem of bus-driven floorplanning is addressed. Given a set of blocks and bus specifications (the width of each bus and the blocks that the bus need to go through), we will generate a floorplan solution such that all the buses go through their blocks, with the area of the floorplan and the total area of the buses minimized. The approach proposed is based on a simulated annealing framework. Using the sequence pair representation, we derived and proved some necessary conditions for feasible buses, for which we allow 0-bend, one-bend, or two-bend. A checking will be performed to identify those buses that cannot be placed simultaneously. Finally, a solution will be generated giving the coordinates of the modules and the buses. Comparing with the results of the most updated work on this problem by Xiang et al. [Bus-driven floorplanning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 2003, pp. 66–73], our algorithm can handle buses going through many blocks and the dead space of the floorplan obtained is also reduced. For example, if the buses have to go through more than 10 blocks, the approach in Xiang et al. [Bus-driven floorplanning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 2003, pp. 66–73] is not able to generate any solution while our algorithm can still give solutions of good quality.

An evolutionary optimization based on the immune system and its application to the VLSI floor-plan design problem

An evolutionary optimization based on the immune system and its application to the VLSI floor-plan design problem

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization

Three-dimensional (3-D) IC physical design problems are usually of higher complexity, with a greatly enlarged solution space due to multiple device structure. In this paper, a new 3-D floorplanning algorithm is proposed for wirelength optimization. Our main contributions and results can be summarized as follows. First, a new hierarchical flow of 3-D floorplanning with a new inter-layer partitioning method. The blocks are partitioned into different layers before floorplanning. A simulated annealing (SA) engine is used to partition blocks with the objective of minimizing the statistical wirelength estimation results. The solution quality is not degraded by the hierarchical flow. Second, floorplans of all the layers are generated in a SA process. Original 3-D floorplanning problem is transformed into solving several 2-D floorplanning problems simultaneously. The solution space is scaled down to maintain a low design complexity. Finally, Experimental results show that our algorithm improves wirelength by 14%-51% compared with previous 3-D floorplanning algorithms. The hierarchical approach is proven to be very efficient and offers a potential way for high-performance 3-D design

A Test Scheduling Algorithm Based on Two-Stage GA

In this paper, we present a new algorithm to co-optimize the core wrapper design and the SOC test scheduling. The SOC test scheduling problem is first formulated into a twodimension floorplan problem and a sequence pair architecture is used to represent it. Then we propose a two-stage GA (Genetic Algorithm) to solve the SOC test scheduling problem. Experiments on ITC'02 benchmark show that our algorithm can effectively reduce test time so as to decrease SOC test cost.

Modeling and simulating coverage in sensor networks

The coverage problem in wireless sensor network is to place sensor devices in a service area so that the entire service area is covered. We have modeled the coverage problem as two sub-problems: floorplan and placement. The floorplan problem is to partition the service area into well-defined geometric cells, where the placement problem is to assign the sensor devices into a set of cells. Our proposed model has transformed the search space from a continuous into discrete, where the cardinality of the set of cells represents all possible candidate locations to place the sensors. Thus, we have reduced the complexity of the coverage problem, but we have had to merge the two sub-problems (floorplan and placement) into a single optimization problem to achieve good solutions. The objective function is to maximize the coverage of the service area while not exceeding a given budget. The merged optimization problem has been coded into an evolutionary approach and our results present an interesting finding between the cell size and sensor’s radius of coverage.

An orthogonal simulated annealing algorithm for large floorplanning problems

The conventional simulated annealing with some random generation mechanism using the sequence-pair topological representation in block placement and floorplanning is effective for a very small number of modules (40-50). This paper proposes an orthogonal simulated annealing algorithm (OSA) with an efficient generation mechanism (EGM) for solving large floorplanning problems. EGM samples a small number of representative floorplans and then efficiently derives a high-performance floorplan by using a systematic reasoning method for the next move of OSA based on orthogonal experimental design. Furthermore, an improved swap operation is proposed which cooperates with EGM to make OSA efficient. Excellent experimental results using the Microelectronics Center of North Carolina and the Gigascale Systems Research Center benchmarks show that OSA performs better than existing methods for large floorplanning problems.

Fixed-outline floorplanning: enabling hierarchical design

Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show that instances of the fixed-outline floorplan problem are significantly harder than related instances of classical floorplan problems. We suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context. Wirelength improvements and optimization of aspect ratios of soft blocks are explicitly addressed by these techniques. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported . A similar slack computation is possible with many other floorplan representations. In all cases the computation time approximately doubles. Our empirical evaluation is based on a new floorplanner implementation Parquet-1 that can operate in both outline-free and fixed-outline modes. We use Parquet-1 to floorplan a design, with approximately 32000 cells, in 37 min using a top-down, hierarchical paradigm.

A linear programming-based algorithm for floorplanning in vlsi design

In this paper, we consider a floorplanning problem in the physical design of very large scale integration. We focus on the problem of placing a set of blocks (modules) on a chip with the objective of minimizing area of the chip as well as total wire length. The blocks have different areas and their shapes are either fixed (predetermined) or flexible (to be determined). We use the sequence-pair suggested by Murata et al. (see ibid, vol.15, no.12, p.1518-1524, 1996) to represent the topology of nonslicing floorplans and present two methods to obtain a floorplan from a sequence-pair. One is a construction method, and the other is a method based on a linear programming model. The two methods are embedded in simulated annealing algorithms, which are used to find a near optimal floorplan. Results of computational experiments on the Microelectronics Center of North Carolina benchmark examples show that the proposed algorithms work better than existing algorithms.

An Attractor-Repeller approach to floorplanning

The floorplanning (or facility layout) problem consists in finding the optimal positions for a given set of modules of fixed area (but perhaps varying height and width) within a facility such that the distances between pairs of modules that have a positive connection cost are minimized. This is a hard combinatorial optimization problem; even the restricted version where the shapes of the modules are fixed and the optimization is taken over a fixed finite set of possible module locations is NP-hard. In this paper, we extend the concept of target distance introduced by Etawil and Vannelli and apply it to derive the AR (Attractor-Repeller) model which is designed to improve upon the NLT method of van Camp et al. This new model is designed to find a good initial point for the Stage-3 NLT solver and has the advantage that it can be solved very efficiently using a suitable optimization algorithm. Because the AR model is not a convex optimization problem, we also derive a convex version of the model and explore the generalized target distances that arise in this derivation. Computational results demonstrating the potential of our approach are presented.

On the approximability of two tree drawing conventions

We consider two aesthetic criteria for the visualization of rooted trees: inclusion and tip-over. Finding the minimum area layout according to either of these two standards is an NP-hard task, even when we restrict ourselves to binary trees. We provide a fully polynomial time approximation scheme for this problem. This result applies to any tree for tip-over layouts and to bounded degree trees in the case of the inclusion convention. We also prove that such restriction is necessary since, for unbounded degree trees, the inclusion problem is strongly NP-hard. Hence, neither a fully polynomial time approximation scheme nor a pseudopolynomial time algorithm exists, unless P=NP. Our technique, combined with the parallel algorithm by Metaxas et al. [Comput. Geom. 9 (1998) 145–158], also yields an NC fully parallel approximation scheme. This latter result holds for inclusion of binary trees and for the slicing floorplanning problem. Although this problem is in P, it is unknown whether it belongs to NC or not. All the above results also apply to other size functions of the drawing (e.g., the perimeter).