Problem Of Parallel Processing Research Articles

FPGA-based multi-channel thermocouple temperature measurement system

Aiming at the high and low temperature test requirements of spacecraft before being sent into space, this paper designs and implements a multi-channel thermocouple temperature measurement system based on FPGA.The system adopts thermocouple as temperature sensor, and ADT7310 is used as thermocouple cold junction temperature compensation, which solves the problem of thermocouple cold junction compensation better.The front end adopts AD7193, a 24-bit analog-to-digital converter with low noise, multi-channel and low power consumption, to amplify and A/D convert the signal at measuring junction of thermocouple.The control core is a field programmable logic gate array FPGA, which can better solve the problem of parallel processing of multi-channel temperature signals. At the same time, it uses the transposition method of the thermocouple standard graduation table, the interpolation look-up table algorithm and the cold junction compensation reverse look-up table algorithm, which is effective The temperature measurement accuracy of each channel is improved.The experimental results show that the system can be connected to 24 K-type or T-type thermocouple sensors, the measurement range can reach -200°C∼220°C (73.15K∼493.15K), and the relative error is less than ±0.3%F.S.

Linda implementations in Java for concurrent systems

AbstractThis paper surveys a number of the implementations of Linda that are available in Java. It provides some discussion of their strengths and weaknesses, and presents the results from benchmarking experiments using a network of commodity workstations. Some extensions to the original Linda programming model are also presented and discussed, together with examples of their application to parallel processing problems. Copyright © 2004 John Wiley & Sons, Ltd.

Static scheduling algorithms for allocating directed task graphs to multiprocessors

Static scheduling of a program represented by a directed task graph on a multiprocessor system to minimize the program completion time is a well-known problem in parallel processing. Since finding an optimal schedule is an NP-complete problem in general, researchers have resorted to devising efficient heuristics. A plethora of heuristics have been proposed based on a wide spectrum of techniques, including branch-and-bound, integer-programming, searching, graph-theory, randomization, genetic algorithms, and evolutionary methods. The objective of this survey is to describe various scheduling algorithms and their functionalities in a contrasting fashion as well as examine their relative merits in terms of performance and time-complexity. Since these algorithms are based on diverse assumptions, they differ in their functionalities, and hence are difficult to describe in a unified context. We propose a taxonomy that classifies these algorithms into different categories. We consider 27 scheduling algorithms, with each algorithm explained through an easy-to-understand description followed by an illustrative example to demonstrate its operation. We also outline some of the novel and promising optimization approaches and current research trends in the area. Finally, we give an overview of the software tools that provide scheduling/mapping functionalities.

Scheduling data-flow graphs via retiming and unfolding

Loop scheduling is an important problem in parallel processing. The retiming technique reorganizes an iteration; the unfolding technique schedules several iterations together. We combine these two techniques to obtain a static schedule with a reduced average computation time per iteration. We first prove that the order of retiming and unfolding is immaterial for scheduling a data-flow graph (DFG). From this nice property, we present a polynomial-time algorithm on the original DFG, before unfolding, to find the minimum-rate static schedule for a given unfolding factor. For the case of a unit-time DFG, efficient checking and retiming algorithms are presented.

MULTIPLUS: A modular high-performance multiprocessor

The MULTIPLUS project which is currently under development at NCE/UFRJ, Brazil, aims at the study of parallel processing problems in MIMD environments. The project includes the development of a parallel shared-memory architecture and a UNIX[+]-like operating system called MULPLIX. The MULTIPLUS architecture uses an inverted n-cube multistage network to interconnect clusters of processing nodes designed around a double-bus system. As a consequence, the architecture is partitionable and modular. It can easily and efficiently support configurations ranging from workstations to powerful parallel supercomputers with up to 2048 processing nodes. The MULPLIX operating system provides MULTIPLUS with an efficient computing environment for parallel scientific applications. MULPLIX uses the concept of thread, implements busy-waiting synchronization primitives very efficiently and carefully considers data locality and scientific processing requirements in the policies adopted for memory management and thread scheduling.