Error Propagation Probability Research Articles

Improved Weighted Volterra DFE for C-Band 100-Gbit/s PAM-4 Transmission Over 60-km SSMF

To cope with the nonlinear distortions and the chromatic dispersion (CD) induced power fading in double-side band (DSB) intensity modulation and direct detection (IM/DD) transmission systems, high-performance Volterra decision-feedback equalizers (VDFEs) are widely applied. However, similar as linear DFE, the VDFEs suffer from error propagation in the case of wrong decisions. In this letter, to reduce the error propagation probability of VDFEs, we propose and experimentally demonstrate a diagonally-pruned improved weighted VDFE (DP-IWVDFE) in a C-band 4-level pulse amplitude modulation (PAM-4) transmission system. By replacing the hard-decision output by the soft-decision feedback symbol based on a compressed sigmoid nonlinear function in DP-IWVDFE, the error propagation probability can be significantly reduced, which lowers the bit error ratio (BER) by a factor of around two as compared to the DP-VDFE. Besides, 100-Gbit/s PAM-4 transmission over 60-km standard single-mode fiber (SSMF) using DP-IWVDFE is realized with the achieved BER below 3.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 10^{-3}$ </tex-math></inline-formula> , achieving around 3.8-dB, 1.5-dB, and 1-dB improvements of the receiver sensitivity over the polynomial DFE (PDFE), improved weighted PDFE (IWPDFE), and DP-VDFE, respectively.

Fast Error Propagation Probability Estimates by Answer Set Programming and Approximate Model Counting

Fast Error Propagation Probability Estimates by Answer Set Programming and Approximate Model Counting

C-band 120-Gb/s PAM-4 transmission over 50-km SSMF with improved weighted decision-feedback equalizer

An improved weighted decision-feedback equalizer (IWDFE) is adopted and experimentally demonstrated to mitigate chromatic dispersion (CD) induced power fading for C-band four-level pulse amplitude modulation (PAM-4) system. Based on a compressed sigmoid nonlinear function, the IWDFE is superior to the conventional DFE, rule-1 and rule-2 based WDFEs in reducing both the error propagation probability and percentage of errors. The IWDFE is combined with a feed-forward equalizer (FFE) to deal with both pre-cursor and post-cursor interference simultaneously. We also introduce 2nd-order polynomial nonlinear terms in both FFE and IWDFE at receiver side, constructing a nonlinear FFE-IWDFE (N-FFE-IWDFE) to simultaneously equalize both the CD-induced power fading and nonlinear distortions. Experimental results show that compared with nonlinear FFE-DFE (N-FFE-DFE), rule-1 and rule-2 based nonlinear FFE-WDFEs (N-FFE-WDFEs), the N-FFE-IWDFE can significantly reduce the bit error ratio (BER), which is close to that of the error-propagation-free N-FFE-DFE. By utilizing the N-FFE-IWDFE, 120-Gb/s PAM-4 transmission system over 50-km standard single-mode fiber (SSMF) is realized with the BER below 7% hard-decision forward error correction (HD-FEC) limit of 3.8 × 10−3, achieving around 1.1-dB improvement of the receiver sensitivity over the N-FFE-DFE. To the best of our knowledge, this is the first time that an IWDFE is employed for C-band IM/DD optical transmission system.

BER-based relay selection strategy for cooperative communication

In this paper, a bit error ratio (BER)-based relay selection strategy is investigated under opportunistic relay selection. The challenging problem is to design the relay selection rule so that the relay is able to measure the performance of the cooperative system at the destination exactly with low computation costs. This paper derives a closed-form expression of the end-to-end bit error rate firstly. Then, an approximate BER expression based on the relationship between the instantaneous signal-to-noise ratio (SNR) of the relay-to-destination link and the probability of error propagation is derived. Finally, a simplified relay selection formula is proposed. Simulation results prove that the proposed relay selection rule can reflect the BER of each relay properly as well.

Special section: Extended papers from REFSQ 2018

Context:Testing is the main validation technique used to increase the reliability of software systems. The effectiveness of testing can be strongly reduced by Failed Error Propagation. This situation happens when the System Under Test executes a faulty statement, the state of the system is affected by this fault, but the expected output is observed. Squeeziness is an information theoretic measure designed to quantify the likelihood of Failed Error Propagation and previous work has shown that Squeeziness correlates strongly with Failed Error Propagation in white-box scenarios. Despite its usefulness, this measure, in its current formulation, cannot be used in a black-box scenario where we do not have access to the source code of the components.Objective:The main goal of this paper is to adapt Squeeziness to a black-box scenario and evaluate whether it can be used to estimate the likelihood that a component of a software system introduces Failed Error Propagation.Method: First, we defined our black-box scenario. Specifically, we considered the Failed Error Propagation that a component introduces when it receives its input from another component. We were interested in this since such fault masking makes it more difficult to find faults in the previous component when testing. Second, we defined our notion of Squeeziness in this framework. Finally, we carried out experiments in order to evaluate our measure.Results: Our experiments showed a strong correlation between the likelihood of Failed Error Propagation and Squeeziness.Conclusion: We can conclude that our new notion of Squeeziness can be used as a measure that estimates the probability of Failed Error Propagation being introduced by a component. As a result, it has the potential to be used as a measure of testability, allowing testers to assess how easy it is to test either the whole system or a single component. We considered a simple model (Finite State Machines) but the notions and results can be extended/adapted to deal with more complex state-based models, in particular, those containing data.

Using Squeeziness to test component-based systems defined as Finite State Machines

Abstract Context:Testing is the main validation technique used to increase the reliability of software systems. The effectiveness of testing can be strongly reduced by Failed Error Propagation. This situation happens when the System Under Test executes a faulty statement, the state of the system is affected by this fault, but the expected output is observed. Squeeziness is an information theoretic measure designed to quantify the likelihood of Failed Error Propagation and previous work has shown that Squeeziness correlates strongly with Failed Error Propagation in white-box scenarios. Despite its usefulness, this measure, in its current formulation, cannot be used in a black-box scenario where we do not have access to the source code of the components. Objective:The main goal of this paper is to adapt Squeeziness to a black-box scenario and evaluate whether it can be used to estimate the likelihood that a component of a software system introduces Failed Error Propagation. Method: First, we defined our black-box scenario. Specifically, we considered the Failed Error Propagation that a component introduces when it receives its input from another component. We were interested in this since such fault masking makes it more difficult to find faults in the previous component when testing. Second, we defined our notion of Squeeziness in this framework. Finally, we carried out experiments in order to evaluate our measure. Results: Our experiments showed a strong correlation between the likelihood of Failed Error Propagation and Squeeziness. Conclusion: We can conclude that our new notion of Squeeziness can be used as a measure that estimates the probability of Failed Error Propagation being introduced by a component. As a result, it has the potential to be used as a measure of testability, allowing testers to assess how easy it is to test either the whole system or a single component. We considered a simple model (Finite State Machines) but the notions and results can be extended/adapted to deal with more complex state-based models, in particular, those containing data.

Soft Error Susceptibility Analysis for Sequential Circuit Elements Based on EPPM

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS’89 benchmark circuits show that our method is more accurate and efficient than previous methods.

Single-Event-Upset Mitigation Placement and Routing Algorithms for Field-Programmable Gate Arrays

To reduce the effects of single-event upsets (SEUs) on field-programmable gate arrays (FPGAs), we propose anti-VPR, an anti-SEU algorithm. The Anti-VPR algorithm is based on VPR, a popular placement and routing tool. The proposed algorithm optimizes the FPGA place cost function and reduces the occurrence of errors, such as open circuit error and short circuit error, by computing the error propagation probability and node error rate of the Configurable Logic Blocks. The Anti-VPR algorithm is implemented and tested on several MCNC benchmark circuits. Experimental results show that the proposed Anti-VPR algorithm achieves a 36.2% greater reduction of sensitive bits compared with the original VPR algorithm without the need for extra hardware overhead, unlike the traditional TMR approach.

Sphere Detection Technique: An Optimum Detection Scheme for MIMO System

In this paper, various multiple input and multiple output (MIMO) detection techniques have been compared on the basis of BER performance and complexity. Maximum likelyhood (ML) detection method has shown optimal solution in MIMO systems compared to conventional detection techniques. However, higher receiver complexity leads to use of lower complexity techniques such as zero forcing (ZF) and minimum mean square error (MMSE) having relatively poor performance. Successive interference cancellation combined with ZF or MMSE has much improved performance but vulnerable to error propagation. Ordered succesive interference cancellation with MMSE (MMSE-OSIC) has reduced error propagation probability and gave the better performance. A new detection technique sphere detection (SD) based on Schnorr-Euchner enumeration has provided ML solution with much less computational complexity. For simulation, Rayleigh channel model has been considered.

SOFT ERROR RATE ESTIMATION FOR COMBINATIONAL LOGIC IN PRESENCE OF SINGLE EVENT MULTIPLE TRANSIENTS

Fast and accurate estimation of soft error rate in VLSI circuits is an essential step in a soft error tolerant ASIC design. In order to have a cost effective protection against radiation effects in combinational logics, an accurate and fast method for identification of most susceptive gates and paths is needed. In this paper, an efficient, fast and accurate method for soft error propagation probability (SEPP) estimation is presented and its performance is evaluated. This method takes into account all three masking factors in multi cycles. It also considers multiple event transients as a new challenge in soft error tolerant VLSI circuit design. Compared with Monte Carlo (MC) simulation-based fault injection method, our SEPP estimation method has a high level of accuracy (with less than 2% difference) while offering 1000× speedup as compared with MC-based simulation.

Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs

As the feature size shrinks to the nanometer scale, SRAM-based FPGAs will become increasingly vulnerable to soft errors. Existing reliability-oriented placement and routing approaches primarily focus on reducing the fault occurrence probability (node error rate) of soft errors. However, our analysis shows that, besides the fault occurrence probability, the propagation probability (error propagation probability) plays an important role and should be taken into consideration. In this paper, we first propose a cube-based analysis algorithm to efficiently and accurately estimate the error propagation probability. Based on such a model, we propose a novel reliability-oriented placement and routing algorithm that combines both the fault occurrence probability and the error propagation probability together to enhance system-level robustness against soft errors. Experimental results show that, compared with the baseline versatile place and route technique, the proposed scheme can reduce the failure rate by 20.73%, and increase the mean time between failures by 39.44%.

Soft error modeling and remediation techniques in ASIC designs

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.

Performance analysis of the weighted decision feedback equalizer

In this paper, we analyze the behavior of the weighted decision feedback equalizer (WDFE), mainly from filtering properties aspects. This equalizer offers the advantage of limiting the error propagation phenomenon. It is well known that this problem is the main drawback of decision feedback equalizers (DFEs), and due to this drawback DFEs are not used very often in practice in severe channels (like wireless channels). The WDFE uses a device that computes a reliability value for making the right decision and decreasing the error propagation phenomenon. We illustrate the WDFE convergence through its error function. Moreover regarding the filtering analysis, we propose a Markov model of the error process involved in the WDFE. We also propose a way to reduce the number of states of the model. Our model associated with the reduction method permits to obtain several characteristic parameters such as, error propagation probability (appropriate to qualify the error propagation phenomenon), time recovery and error burst distribution. Since the classical DFE is a particular case of the WDFE (where the reliability is always equal to one); our model can be applied directly to DFE. As a result of the analysis of this process, we show that the error propagation probability of the WDFE is less than that of the classical DFE. Consequently, the length of the burst of errors also decreases with this new WDFE. Our filtering model shows the efficiency of the WDFE.

Implementation and Analysis of Probabilistic Methods for Gate-Level Circuit Reliability Estimation

The development of VLSI technology results in the dramatically improvement of the performance of integrated circuits. However, it brings more challenges to the aspect of reliability. Integrated circuits become more susceptible to soft errors. Therefore, it is imperative to study the reliability of circuits under the soft error. This paper implements three probabilistic methods (two pass, error propagation probability, and probabilistic transfer matrix) for estimating gate-level circuit reliability on PC. The functions and performance of these methods are compared by experiments using ISCAS85 and 74-series circuits.

Sensitivity to errors in artificial neural networks: a behavioral approach

The problem of sensitivity to errors in artificial neural networks is discussed here considering an abstract model of the network and the errors that can affect a neuron's computation. Feed-forward multilayered networks are considered; the performance taken into account with respect to error sensitivity is their classification capacity. The final aim is evaluation of the probability that a single neuron's error will affect both its own classification capacity and that of the whole network. A geometrical representation of the neural computation is adopted as the basis for such evaluation. Probability of error propagation is evaluated with respect to the single neuron's output as well as to the complete network's output. The information derived is used to evaluate, for a specific digital network architecture, the most critical sections of the implementation as far as reliability is concerned and thus to point out candidates for ad-hoc fault-tolerance policies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>