Presence Of Parasitic Capacitance Research Articles

Anti-Series Varactor Network With Improved Linearity Performances in the Presence of Inductive and Capacitive Parasitics

This paper proposes a varactor-based circuit technique intended for amplitude and phase control, with improved linearity in the presence of parasitic capacitances and parasitic inductances. The mechanism causing linearity degradation in an anti-series varactor network that includes significant parasitic elements - a key aspect that, to our knowledge, has never been reported - is first studied using an analytical approach based on multi-tone excitation. It is demonstrated that simply optimizing the ratio of diode sizes is insufficient to circumvent this linearity degradation. The underlying linearity degradation concept serves as the basis for the introduction of a modified anti-series controllable capacitance, followed by a design and practical implementation. Experimental validations with multi-tone and modulated signals demonstrate improved linearity performances with respect to the state-of-the-art when parasitic capacitances and inductances are significant. Moreover, it is shown that the complete varactor-based circuit topology proposed here, which uses the proposed modified anti-series controllable capacitance in conjunction with a second-harmonic trap filter, constitutes a very attractive alternative to the state-of-the-art anti-series/anti-parallel topology, since it reduces the required number of diodes by a factor of 2. Measurements on discrete-component designs operating at 3.6GHz, hence with significant parasitic effects, demonstrate that the proposed circuit topology improves the 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> order intermodulation distortion levels by 10.6dB and 6.6dB at output powers of 10dBm and 18dBm respectively, in comparison with the state-of-the-art topology. Measurements with a 16QAM modulated signal also show 3.9dB improvement in ACPR at 18dBm. These performances constitute improved state-of-the-art results in anti-series hyper-abrupt varactor-based electronic control.

Analysis of Maximum Voltage Transient of JT-60SA Toroidal Field Coils in Case of Fast Discharge

The voltage transient appearing across and inside the toroidal field (TF) coils of JT-60SA in case of fast voltage variation, such as a safety discharge operated by the quench protection circuit (QPC), can be significantly high. In fact, the voltage distribution between coils and inside the winding can be not uniform during fast transient, being influenced by the presence of parasitic capacitances. A simplified electrical model of the TF coils has been developed to investigate this aspect. Its robustness has been proved by means of parametric sensitivity analysis, and the impact of the included simplifications has been evaluated. The obtained model has been used in conjunction with an electrical model of the TF circuit elements, including a simplified model of the QPC able to reproduce the voltage appearing across its terminals as observed during experimental operation of the QPC prototype. The worst case in terms of transient voltage applied to the winding has been identified, corresponding to a fault to ground occurring just after QPC operation. It has been verified that the resulting voltage is largely inside the coil insulation capability defined by performed insulation voltage tests.

Wpływ pojemności pasożytniczych transoptora na sterowanie tranzystorami w przekształtniku impulsowym

Optocouplers are widely used, e.g. in the switching converters, in which they are used to obtain electrical isolation between gate transistors circuits and microprocessor controller. In transoptors exists parasitic capacitances which couples output and input circuits of the system. The influence of these capacitances is negligible for most applications. However, in switching converters, where the potentials of the input and output circuit of an optocoupler changes very fast, the presence of parasitic capacitances can lead to the distortion of transistors control signals. The paper discusses the general structure, key features and parameters of digital optocouplers. Cause and location of parasitic capacitances was shown in a simulation model of optocoupler, which takes into account the parasitic capacitances was designed. Simulation results illustrating the impact of capacitance and rate of voltage change to waveform of the transistors control signals were presented. Shows selected results of laboratory verification

Assessment of high-frequency performance limits of graphene field-effect transistors

High frequency performance limits of graphene field-effect transistors (FETs) down to a channel length of 20 nm have been examined by using self-consistent quantum simulations. The results indicate that although Klein band-to-band tunneling is significant for sub-100 nm graphene FETs, it is possible to achieve a good transconductance and ballistic on-off ratio larger than 3 even at a channel length of 20 nm. At a channel length of 20 nm, the intrinsic cut-off frequency remains at a few THz for various gate insulator thickness values, but a thin gate insulator is necessary for a good transconductance and smaller degradation of cut-off frequency in the presence of parasitic capacitance. The intrinsic cut-off frequency is close to the LC characteristic frequency set by graphene kinetic inductance (L) and quantum capacitance (C), which is about 100 GHz·μm divided by the gate length.

A Locally Amplified Strain Sensor Based on a Piezoelectric Polymer and Organic Field-Effect Transistors

Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation, which have complicated the development of array-based polyvinylidene difluoride (PVDF) sensors. We have used organic field-effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer, i.e., PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal, which can be detected even in the presence of parasitic capacitance. The device couples the voltage generated by the PVDF film under strain into the gate of organic thin-film transistors using an arrangement that allows the full piezoelectric voltage to couple to the channel while also increasing charge-retention time. A bipolar detector is created using ultraviolet-ozone treatment to shift the threshold voltage and increase the current of the transistor under both compressive and tensile strain. An array of devices that maps the strain field on a PVDF film surface is demonstrated.

On the parasitic-sensitivity of switched-capacitor summing-integrator structures for ΣΔ modulators

This brief focuses on the comparative analysis of the parasitic sensitivity of different switched-capacitor summing-integrator structures employed in /spl Sigma//spl Delta/ modulators. One summing-integrator structure with cross-coupled switches is found to be parasitic sensitive, whereas that without cross-coupled switches is found to be parasitic insensitive. The effect of parasitic-sensitive and parasitic-insensitive summing integrators on the performance of a second-order /spl Sigma//spl Delta/ modulator is reported. Circuit simulations indicate a degradation of the signal-to-noise-plus-distortion ratio (SNDR) of the modulator from 89 dB to as low as 51 dB in the presence of certain parasitic capacitances when the parasitic sensitive summing integrator is used. This is primarily due to a prominent second-harmonic component in the quantizer output. Simulations using the parasitic-insensitive summing-integrator structure are found to cause no prominent harmonic distortion and, hence, no degradation of the SNDR in the presence of any parasitic capacitances.

Design and Analytical Study of Strays-Insensitive Switched-Capacitor Filters

Use of analog circuit elements in active networks have become very common and the demand for their miniaturization is increasing day by day. Though several methods are available for the miniaturization of these elements through large scale integration on single chips, the performance is not very satisfactory in low-frequency applications, due to the presence of parasitic capacitance that is comparable to the capacitance of active elements. As a result, the desired response gets deviated and also noise is involved. In this paper, an attempt has been made to devise methods for the elimination or reduction of the influence of these parasitic capacitances on filter circuits.

Efficient design centering of analog integrated circuits using binary search

This paper introduces a procedure for automatically design centering analog integrated circuits called the divide-and-focus method (DAF). DAF is a simple, efficient, and effective algorithm for design centering complex circuits, even if the performance of the original nominal design is poor. DAF uses a binary search of each dimension of parameter space to rapidly focus on regions promising high yield. DAF was applied to a third-order elliptic CMOS transconductance-C integrated circuit filter derived from an automated layout and containing 126 nodes and 319 MOSFETS. Using five key capacitor values as design centering parameters, DAF improved yield in the presence of parasitic capacitance (as extracted from the layout) by a factor of 19 from an initial value of 4% to a final value of 76%. By relaxing constraints on component value symmetry, DAF found a higher yield than was possible when maintaining symmetry, where DAF achieved a yield of 34%. Since DAF uses Monte Carlo analysis to estimate circuit yield, its execution time can be further reduced by exploiting the parallelism implicit in Monte Carlo techniques. Using a local area network of 10 workstations similar to those available at most engineering sites, DAF completed the design centering of the filter 7.4 times faster than when using a single workstation.

Simplified MOS switched capacitor ladder filter structures

A general technique for time-sharing amplifiers to reduce die area in switched capacitor ladder filters is described and illustrated with a fifth-order elliptic low-pass ladder filter requiring only three operational amplifiers. Techniques for synthesizing filters with maximum passband accuracy in the presence of parasitic capacitances are presented, and verified with two versions of the same fifth-order design integrated in a standard NMOS process. Passband accuracies of better than 0.1 dB have been achieved using only 0.3 pF unit-sized capacitors. The dynamic range is 75 dB.