Preparation Of Thin Film Transistors Research Articles

Fabrication and Properties of InGaZnO Thin-Film Transistors Based on a Sol-Gel Method with Different Electrode Patterns.

The preparation of thin-film transistors (TFTs) with InGaZnO (IGZO) channels using sol-gel technology has the advantages of simplicity in terms of process and weak substrate selectivity. We prepared a series of TFT devices with a top contact and bottom gate structure, in which the top contact was divided into rectangular and circular structures of drain/source electrodes. The field-effect performance of TFT devices with circular pattern drain/source electrodes was better than that with a traditional rectangular structure on both substrates. The uniform distribution of the potential in the circular electrode structure was more conducive to the regulation of carriers under the same channel length at different applied voltages. In addition, with the development of transparent substrate devices, we also constructed a hafnium oxide (HfO2) insulation layer and an IGZO active layer on an indium tin oxide conductive substrate, and explored the effect of circular drain/source electrodes on field-effect properties of the semitransparent TFT device. The IGZO deposited on the HfO2 dielectric layer by spin-coating can effectively reduce the surface roughness of the HfO2 layer and optimize the scattering of carriers at the interface in TFT devices.

Stepped Annealed Inkjet-Printed InGaZnO Thin-Film Transistors

The preparation of thin-film transistors (TFTs) using ink-jet printing technology can reduce the complexity and material wastage of traditional TFT fabrication technologies. We prepared channel inks suitable for printing with different molar ratios of their constituent elements. Through the spin-coated and etching method, two different types of TFTs designated as depletion and enhancement mode were obtained simply by controlling the molar ratios of the InGaZnO channel elements. To overcome the problem of patterned films being prone to fracture during high-temperature annealing, a stepped annealing method is proposed to remove organic molecules from the channel layer and to improve the properties of the patterned films. The different interfaces between the insulation layers, channel layers, and drain/source electrodes were processed by argon plasma. This was done to improve the printing accuracy of the patterned InGaZnO channel layers, drain, and source electrodes, as well as to optimize the printing thickness of channel layers, reduce the defect density, and, ultimately, enhance the electrical performance of printed TFT devices.

Self-patterning of high-performance thin film transistors

We have developed a technique for the preparation of thin film transistors (TFTs) through the self-patterning of various organic and inorganic materials via solution processing using a wide range of solvents. To obtain selectively self-patterned layers, we treated the oxide dielectric with two-phase patterned self-assembled monolayers of hexamethyldisilazane (HMDS) and octyltrichlorosilane. The conducting polymer poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulfonic acid) in water and the dielectric polymer poly(vinyl phenol) in propylene glycol methyl ether acetate were both selectively deposited and patterned on the HMDS regions with high-quality feature shapes. When source and drain electrodes were patterned on the bottom-gate oxide wafer, we also self-patterned organic and inorganic semiconductors around the channel (HMDS) regions. These TFT devices exhibited moderate to good electronic characteristics. This method has great potential for the economical full solution processing of large-area electronic devices. The selectivity in the patterning phenomena can be understood in terms of surface energy interactions.

Preparation of thin-film transistors with chemical bath deposited CdSe and CdS thin films

The authors have fabricated the thin-film transistor (TFT) with CdSe and CdS semiconductor thin films, prepared by a low temperature chemical bath deposition (CBD) method, as an active layer. The ON-current values of the CdSe-TFTs and CdS-TFTs at a gate bias of 10 V and a source-drain voltage of 10 V are about 100 /spl mu/A and 5 /spl mu/A, respectively. The OFF-current values of the CdSe-TFTs and CdS-TFTs at the source-drain voltage of 10 V are less than 10 pA. The fabricated CdSe-TFTs exhibited a field effect mobility of 15 cm/sup 2//V-s, threshold voltage of 3.5 V, subthreshold slope of 0.5 V/dec., and ON/OFF current ratios exceed 10/sup 7/. A field effect mobility of I cm/sup 2//V-s, a threshold voltage of 2.6 V, a subthreshold slope of 0.6 V/dec., and an ON/OFF current ratios exceed 10/sup 6/ were observed for CdS TFTs.