Pre-gate Cleaning Research Articles

Dewetting Model Study on a Spinning Substrate - Challenges for Low Chemical Consumption

Continuous device shrinkage beyond 3X and 2X nm increases the number of critical clean processes in semiconductor manufacturing. In order to avoid cross contamination from reclaimed chemistry, single-pass chemistry has become more commonly used. This migration to single-pass started in the FEOL pre-gate cleaning process. In recent years, some BEOL clean processes have also started using single-pass due to the risk of defect formation on wafer surfaces with reclaimed chemistries. The major drawback of single- pass is the cost of the chemistry. In an effort to contain this higher cost, processes with lower medium flow rates are rapidly becoming more popular. In this paper, the risks associated with lower flow processes are discussed. Single-wafer spin clean tools have been widely used in semiconductor manufacturing. In processes where mass transport is not the rate limiting step, reducing chemical consumption can be achieved by decreasing the medium flow rate. This approach yields acceptable results when the process is operated near ambient temperature or heating is provided by a substrate heater. The other risk associated with low flow processes is wafer surface dewetting which may result in non-uniform etching and/or reduces cleaning efficiency. A dewetting model for single wafer spin clean process has been developed to predict the process window of low flow processes. Based on this model, the minimum required medium flow rate to completely wet a surface with various contact angle is calculated. Good agreement between model predictions and experimental observations have been obtained. Model The phenomenon of dewetting on a stationary surface has been studied in detail [1]. However, there is very limited information in the published literature on this topic on a spinning surface. On such a surface, a dynamical balance exists between the flowing liquid with the surface and interfacial energies. In this paper, this balance is characterized by the wetting and dewetting velocities. The liquid wetting velocity is modeled as the liquid radial flow velocity (Ur) at the air/liquid interface and is approximated by the following expression Eq.1where w is the substrate rotational speed, r is the radial distance from the wafer center, h is the thickness of the liquid film which is a function of the liquid volumetric flow rate (Q), and ν is the kinematic viscosity. An empirically corrected film thickness expression can be found in ref. [2]. The force balance that takes place on the dewetting front is illustrated in Fig.1. The dewetting driving energy, ED , is given by Eq.2where gL is the liquid surface tension, g SL the solid/liquid interfacial energy, g So the dry solid surface energy, r the mass density of the liquid, g the gravitational acceleration, and Ud the dewetting velocity. It can be shown that the ratio between the wetting and dewetting velocities is given by Eq.3where hc is the critical dewetting thickness which is a function of the contact angle and the capillary length. A dynamical balance between wetting and dewetting is reached when these two velocities equal to each other thus defining the minimum flow rate required to maintain a wetted surface. The model predicted minimum wetting flow rate as a function of the contact angle calculated at various rotational speeds is shown in Fig. 2 Experimental As examples to demonstrate the validity of Fig. 2, 30~40 degree contact angle surfaces were prepared by stripping the native oxide from Si substrates and re-growing chemical oxide using H2O2. Figure 3a shows severe de-wetting at a process condition of 0.1 LPM (Litter Per Minute) and 500 rpm This behavior is expected based on the model results of Fig. 2. The condition of 0.5 LPM and 500 RPM (Fie. 3b) resulted in almost all the surface covered with minor edge de-wetting. This is also consistent to the model result. Dewetting on patterned wafers will also be discussed in this paper. Summary A model has been developed to predict dewetting on single wafer spin processes. Good correlations between model and experimental results were obtained. Leveraging this model is useful for lowering process flow rates on various surface conditions. For example, in the case of a hydrophilic surface, a low flow rate of 0.5 LPM process can be applied which would provide significant cost savings in comparison to the nominal flow rate 1.5 LPM. Eq.3 also gives a numeric guideline on the relative importance of flow rates versus rotation speeds, surface tension, etc.

Three-Step Room-Temperature Cleaning of Bare Silicon Surface for Radical-Reaction-Based Semiconductor Manufacturing

In this study, a cleaning method for pregate cleaning which can suppress the generation of the microroughness of silicon-wafer surfaces as well as remove various contaminations such as metallic impurities, organic materials, and particles has been investigated. Functional waters such as ozonized ultrapure water (-UPW), -added UPW (-UPW), and low-concentration HF and hydrogen peroxide solution have been used in this cleaning method at room temperature. The cleaning-process flow is as follows: (i) -UPW cleaning, (ii) diluted HF and mixture including surfactant molecules (FPMS) cleaning with megasonic, and (iii) 30%-isopropyl alcohol/UPW rinsing, i.e., realization of three-step cleaning. After the pregate cleaning, silicon substrates are set into the radical-reaction gate-insulator film-formation process using microwave-excited, high-density plasma equipment, where or ion bombardment onto the substrate surface has been introduced to eliminate absorbed surfactant molecules as well as hydrogen termination, before starting oxygen radical oxidation or radical nitridation . This advanced, three-step room-temperature cleaning is promising for future semiconductor manufacturing in conjunction with the newly developed radical-reaction-based semiconductor manufacturing.

Surface Preparation for Transistor Performance Improvement in Triple Gate Oxide Integration

Fabrication of current high-performance metal-oxide-semiconductor field effect transistors (MOSFETs) requires a multiple gate oxide integration to obtain different oxide thicknesses and applied voltages. However, channel mobility and drive current are degraded as the number of oxide growth and etching steps increases during the multiple gate oxide integration. In multiple gate oxide integration, a shorter overetch time with a more dilute HF solution for the removal of preexisting oxides exhibits improved surface mobility and transistor drive current resulting from the suppression of surface roughness deterioration. The elimination of SC1 cleaning or the addition of a lower-temperature dilute SC1 cleaning in the pregate cleaning sequence also produces improved transistor mobility. Considering that the addition of SC1 cleaning in the pregate cleaning sequence is needed to remove particles on the surface, the use of a dilute SC1 cleaning may be a realistic method to achieve both improvement of transistor performance and removal of particles. Mobility and drive current of are found to be more sensitive to surface preparation changes than , which may be explained by the closer proximity of electrons to the interface compared to holes.

An Improved Pregate Cleaning Process for High-k Gate Dielectric Fabrication

A novel -last pregate clean process is proposed for high- gate dielectric fabrication. Compared to conventional DHF-last pregate cleaning processes, the use of a novel -last pregate clean process improved Si interfacial thermal stability with and enhanced channel carrier mobility. These improvements in the high- gate stack could be attributed to the more ideal Si surface produced by the treatment.

The Ozone Solubility and its Decay in Aqueous Solutions: Crucial Issues in Ozonated Chemistries for Semiconductor Cleaning

The use of ozone is becoming more and more popular for the cleaning of semiconductor structures, e.g. for pregate cleaning (e.g. thin oxide growth 1 and organic monolayer removal ) and photoresist stripping . Fundamental knowledge about the physicochemical behaviour of ozone in aqueous solutions is a necessity for optimizing these processes. Two crucial parameters are the solubility and the decomposition of ozone in DI-water. The ozone decomposition is driven by a variety of radicals which are formed as reaction products between water, ozone and “impurities”. Moreover these radicals may be more reactive than ozone itself. It is thus of importance to optimize both parameters to achieve the best conditions for each application.

Influence of Pre-Gate Cleaning ON Si/SiO2 Interface and Electrical Performance of Cmos Gate Oxide

AbstractThe Si/SiO2 interface is attracting new interest as gate dielectrics in MOS devices become ultra thin. In this paper, the impact of pre-gate cleaning on the morphology of the Si/SiO2 interface and the electrical performance of CMOS gate oxides has been systematically investigated. Using the High-Resolution Transmission Electron Microscopy (HRTEM) technique, we observed the Si/SiO2 interface at an atomic level. We have found a direct experimental relationship between the pre-gate cleaning scheme, Si/SiO2 interface morphology, and the electrical properties of CMOS gate oxides. When the ratio of H2O2:NH4OH ≥ 1.45, the roughness of the Si/SiO2 interface was dramatically improved, which, in turn, increased the Charge-to-Breakdown to an ideal value.

Performance and Reliability of Scaled Gate Dielectrics

ABSTRACTGate dielectrics for advanced ULSI circuits are rapidly scaling below 10 nm. Thinner dielectrics and smaller lateral dimensions are essential to produce high performance transistors for memories, microprocessors and microcontrollers. In this overview we will discuss the factors that affect the performance and reliability of scaled gate dielectrics. Process parameters that affect oxide and oxynitride dielectrics include substrates, pre-gate cleaning, growth parameters and growth techniques as well as oxide and oxynitride dielectric materials. Thin dielectrics require new or modified measurement methods and extensive use of physical analysis techniques such as SIMS, XPS, AFM and TEM to characterize these materials. Boron diffusion through thin gate oxides, HCI stress, and process induced damage can degrade dielectric quality and affect long term reliability. These factors will affect the performance and reliability of circuits with scaled gate dielectrics.

Synthesis of Ultra-thin stacked oxides using low pressure single furnace cluster process

ABSTRACTThis work describes the development of a new grow-deposit-grow cluster process to grow ultra-thin stacked oxides. Two approaches for stacked oxide synthesis are discussed, namely thermal and chemical stacked oxides. Fabrication of chemical stacked oxide involves forming the first grown layer chemically after pre-gate cleaning, subsequent deposition of a TEOS-SiO2 layer and final densification/oxidation in a single low pressure (LP) furnace operation. In comparison, all three steps for thermal stacked oxide are accomplished by the LP cluster operation. Both processes offer the advantages of reduced cycle time and higher throughput to the stacked gate technology that produces superior Si/SiO2 interfaces and exhibits higher resistance to plasma-damage during ultra large scale integrated circuit (ULSI) processing. The quality and electrical characteristics of the stacked oxides are discussed.

Investigation of the Need for Alternative cleaning Chemistries for 30Å Gate Oxides

ABSTRACTA comparative study of pregate cleaning solution chemistries has been conducted, for 30Å furnace oxides, to investigate the feasibility of continuing to use current cleaning technologies in this thickness range. The experiment focused on correlating changes of device properties with changes in chemistry. Several options were investigated for growing or etching the surface passivation oxide. Chemistries studied included standard SC1 (with Megasonic)/SC2, final HF, as well as room temperature single bath HF based chemistries (HF only, HF+H2O2, HF+HCl, HF+H2O2+HCl, SPM+HF). These chemistries were evaluated in terms of oxidation rate, metallic contamination from solutions, capacitance-voltage (CV) characteristics, and gate oxide integrity. Data suggest that furnace oxides can be reliably grown using conventional cleaning technology. HF-based mixtures might be justified for even more aggressive gate oxide thicknesses.

Utilizing Bath/Wafer Contamination Correlation to Validate a Pre-Gate Cleaning Strategy

ABSTRACTThe correlation of contaminants in a process bath with contaminants on a silicon wafer prepared in the bath is important information when developing a cleaning strategy. In this paper, we present such a correlation focused on contaminants in dilute HF (1:100) and in SC1 (1:1:5 and 1:1:80 at 50°C and 65°C). We have limited the contamination levels to between 0 and 150 ppb. We have also limited the contaminants studied to those that are most likely to be a problem (Fe, Al, Mg, Ca, Cu, Zn, and Na). The bath concentrations are measured using ICPMS and the wafer surface concentrations are measured using both VPD/TXRF and VPD/ICPMS.We demonstrate that Fe and Ca at the levels studied do not deposit from dilute HF, while Cu deposits, showing a linear dependence on bath concentration. We also demonstrate that in the SCl bath, both concentration and temperature are important variables in the contamination of wafers for a given bath contamination level. Al and Zn contaminate wafers most strongly, with Al being the largest contributor at the higher concentration of SC1 and Zn being the largest contributor in the lower concentration. Finally, we demonstrate that a dilute HF clean can remove everything deposited in a highly contaminated SC1 bath.

Front-End Integration Effects on Gate Oxide Quality

AbstractIn this paper, the impact of several front-end processing steps (up to gate oxidation) on gate oxide integrity (GOI) is evaluated. In PBL isolation processing, the use of as-deposited amorphous silicon (a-Si), subsequently annealed during nitride deposition, results in better structural and electrical properties compared to as-deposited polysilicon or as-deposited a-Si with an extra anneal step prior to nitride deposition. Thicker or dual sacrificial schemes exhibit improved gate oxide low voltage breakdown and charge-to-breakdown. Dilute RCA chemistries during pre-gate cleaning produce equal or better surfaces for gate oxidation than the conventional non-dilute RCA with less chemical usage. As gate oxides are scaled below 100Å, lowering gate oxidation temperature is proven to result in far better gate oxide quality than maintaining process temperatures at or above 900°C and diluting oxygen in either argon or nitrogen.