Precision Analog-to-digital Converter Research Articles

Research on Cosine-Sum Windows with Maximum Side-Lobe Decay for High Precision ADC Spectral Testing

Achieving coherent sampling has always been a major challenge in analog-to-digital converter (ADC) spectral testing. If the coherent sampling condition cannot be met, leakage appears in the spectrum, which results in inaccurate parameters. The windowing method is widely used to process ADC data to eliminate leakage. However, this method requires prior knowledge about the type of window, and some commonly used windows cannot provide accurate results for a high precision ADC. In this paper, some general principles for optimizing the cosine-sum window and some windows with maximum side-lobe decay have been presented. A test method for eliminating the leakage caused by non-coherent sampling is also proposed. The proposed method can accurately evaluate the dynamic parameters of an ADC with arbitrary non-coherency. Various simulation results and measurement data demonstrate the functionality and robustness of the proposed method. The proposed method significantly relaxes the condition of coherent sampling and decreases the test cost.

Time-Delay-Neural-Network-Based Audio Feature Extractor for Ultra-Low Power Keyword Spotting

In this brief, we propose an audio feature extractor, based on a time delay neural network (TDNN), for ultra-low power keyword spotting (KWS). Conventionally, mel-frequency cepstrum coefficients (MFCCs) are widely used as features for KWS. However, an analog-to-digital converter (ADC) with high precision and high sampling rate is required for computing MFCCs, which consumes large amount of power. In our proposed feature extractor, on the other hand, input audio signals are band-pass filtered, and then the filtered signals are processed in TDNN in the analog domain, which can substitute a high precision ADC with simple clocked comparators. Simulation results show that the power dissipation of the proposed feature extractor can be reduced by 88% compared to the conventional MFCC feature extractor.

On the performance of double resolution ADC receivers for massive MIMO relaying systems

High power consumption and hardware cost are the two challenges for practical massive MIMO systems. One promising solution is to employ low resolution analog to digital converter (ADC). In this paper, massive MIMO relaying systems are investigated with double resolution ADCs at base station receiver, where some antennas are connected to low resolution ADCs, while the rest of the antennas are connected to high resolution ADCs. Closed form expression for uplink spectral efficiency (SE) is derived using the maximum ratio combining receiver assuming perfect channel state information. Some asymptotic analysis is discussed to explore the effects of system parameters on SE such as; the number of receive antennas, ADC quantization bits, user transmit power and the rate of high precision ADC in double resolution ADC structure. Moreover, energy efficiency with some system parameters is studied. It is shown that the performance wastage owing to low precision ADCs can be recompensed by growing the number of receive antennas $$ \varvec{N} $$, following a logarithmic scaling law instead of increasing the transmit power at both of source and relay. The double resolution ADCs can achieve a better tradeoff between power consumption and SE when using 4 quantization bits. By using only around 30 antennas, the double resolution ADCs achieves its optimal energy efficiency for selecting system parameters.

Quick and cost-efficient A/D converter static characterization using low-precision testing signal

The measurement of the analog-to-digital converter (ADC) output by exciting the signal generator with a high precision input signal allows the determination of ADC's static characteristics using a histogram-based approach. However, this method exhibits some limitations imposed by the input signal, including its high resolution and high linearity that are causes for concern when testing a high precision ADC. Recent research work has been trying to overcome such limitations. Nonetheless, it is necessary to discover a simple and low-cost method to measure the linearity of a high precision ADC through a low precision stimulus. This paper introduces a novel procedure that allows the relaxation of the requirements of the signal source for estimating ADC's linearity characteristics. The proposed method requires two sets of testing sources, being both ramp signals, one of low-precision and the other attenuated. Simulation and experimental results validate the proposed method in different ADCs.

Very linear open-loop CMOS sample-and-hold structure for high precision and high speed ADCs

This paper presents an improved bottom-plate sampling sample-and-hold (S/H) architecture for high speed and high linearity analog to digital converters (ADCs). The proposed circuit reduces the char...

Optimal Subcarrier Power Allocation for OFDM with Low Precision ADC at Receiver

Motivated by the need to reduce power consumption in the receiver analog-to-digital converter (ADC) in multi-Gbps communication systems, in this paper, we study subcarrier power allocation based on channel side information (CSI) at the transmitter. We derive a fixed point equation for subcarrier power allocation that minimizes uncoded symbol error rate (SER) when a finite precision ADC is used at the receiver. We study the sensitivity of the optimal power allocation with respect to a parameter that depends on the ADC precision. Based on this, we propose a simple analytical approximation for the optimal power allocation, which performs within 0.5 dB of the exact case over a wide range of signal-to-noise ratio (SNR). The proposed power allocation leads to only a small increase in the peak-to-average power ratio (PAPR) (< 0.3 dB) for channel models suggested in IEEE 802.15.3c. Further, for a 16-QAM input, 7/8 rate low density parity check (LDPC) code and 3-bit precision ADC, it attains a coded bit error rate (BER) of 10^{-5} at a SNR of 23.5 dB, which compares favorably with the 25 dB required by a traditional system with equal power allocation across the subcarriers and infinite sampling precision. We also show the robustness of the performance gain to channel estimation errors.

자기-자이로 유도 장치를 위한 MEMS형 자이로의 민감도 최적화

This paper presents a sensitivity optimization of a MEMS (microelectromechanical systems) gyroscope for a magnet-gyro system. The magnet-gyro system, which is a guidance system for a AGV (automatic or automated guided vehicle), uses a magnet positioning system and a yaw gyroscope. The magnet positioning system measures magnetism of a cylindrical magnet embedded on the floor, and AGV is guided by the motion direction angle calculated with the measured magnetism. If the magnet positioning system does not measure the magnetism, the AGV is guided by using angular velocity measured with the gyroscope. The gyroscope used for the magnet-gyro system is usually MEMS type. Because the MEMS gyroscope is made from the process technology in semiconductor device fabrication, it has small size, low-power and low price. However, the MEMS gyroscope has drift phenomenon caused by noise and calculation error. Precision ADC (analog to digital converter) and accurate sensitivity are needed to minimize the drift phenomenon. Therefore, this paper proposes the method of the sensitivity optimization of the MEMS gyroscope using DEAS (dynamic encoding algorithm for searches). For experiment, we used the AGV mounted with a laser navigation system which is able to measure accurate position of the AGV and compared result by the sensitivity value calculated by the proposed method with result by the sensitivity in specification of the MEMS gyroscope. In experimental results, we verified that the sensitivity value through the proposed method can calculate more accurate motion direction angle of the AGV.

Accurate Testing of Analog-to-Digital Converters Using Low Linearity Signals With Stimulus Error Identification and Removal

Linearity testing of analog-to-digital converters (ADCs) can be very challenging because it requires a signal generator substantially more linear than the ADC under test. This paper introduces the stimulus error identification and removal (SEIR) method for accurately testing ADC linearity using signal generators that may be significantly less linear than the device under test. In the SEIR approach, two imprecise nonlinear but functionally related excitations are applied to the ADC input to obtain two sets of ADC output data. The SEIR algorithm then uses the redundant information from the two sets of data to accurately identify the nonlinearity errors in the stimuli. The algorithm then removes the stimulus error from the ADC output data, allowing the ADC nonlinearity to be accurately measured. For a high resolution ADC, the total computation time of the SEIR algorithm is significantly less than the data acquisition time and therefore does not contribute to testing time. The new approach was experimentally validated on production test hardware with a commercial 16-bit successive approximation ADC. Integral nonlinearity test results that are well within the device specification of /spl plusmn/2 least significant bits were obtained by using 7-bit linear input signals. This approach provides an enabling technology for cost-effective full-code testing of high precision ADCs in production test and for potential cost-effective chip-level implementation of a built-in self-test capability.