Pre-layout Simulation Results Research Articles

Comprehensive Analytical Comparison of Ring Oscillators in FDSOI Technology: Current Starving Versus Back-Bias Control

Back-bias control is a new degree of freedom brought by fully-depleted silicon-on-insulator (FDSOI) CMOS technologies, which can be used to control the oscillation frequency of voltage-controlled ring oscillators (VCROs). The resulting VCRO architecture is called a back-bias-controlled oscillator (BBCO). This paper compares it with the conventional current-starved ring oscillator (CSRO) topology in terms of power consumption and phase noise figure-of-merit (FoM), while taking practical design constraints of process-voltage-temperature (PVT) robustness and frequency tuning range into account. The proposed comprehensive analysis takes advantage of relevant and compact analytical models, as well as extensive pre-layout simulation results. The comparison is made at four different target oscillation frequencies, which are representative of frequency synthesis for WiFi/Bluetooth/LPWAN wireless communications and of clock generation for smartphone/Internet-of-Things processors: 300 MHz, 868 MHz, 2.45 GHz, and 5.18 GHz. In 28-nm FDSOI technology, the results demonstrate that BBCOs can intrinsically reach 1.69 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.63\times $ </tex-math></inline-formula> lower minimum power consumption and slightly better FoM values than CSROs.

Fully differential fifth-order dual-notch low-pass filter for portable EEG system

This paper presents a new fully differential fifth-order dual-notch low-pass filter based on multiple-input multiple-output operational transconductance amplifiers (MIMO OTA). This work shows that MIMO OTA-based fifth-order dual-notch filter can reduce the number of used OTAs, resulting in simplified realization and low-power consumption. The multiple-input OTA is obtained by using the multiple-input dynamic threshold MOS (DTMOS) technique without additional differential pairs. A simple common-mode feedback technique has been used; thus, fully differential OTA can be easily obtained. The proposed dual-notch low-pass filter can be applied to electroencephalogram (EEG) detection system to reject the 50 Hz powerline interference and the third harmonic 150 Hz. The proposed filter has been simulated using Cadence environment with 0.18 µm TSMC CMOS process. The power supply of 0.5 V is used and the total power consumption of the MIMO OTA is 17.5 nW. The proposed filter provides 49.7 dB dynamic range for 1% total harmonic distortion (THD) for a sine input signal of 250 mVpp at 10 Hz. At 50 Hz and 150 Hz the notch depths of attenuation are respectively −37.2 dB and −47.4 dB. The pre-layout simulation results are in good agreement with the theory.

Asynchronous DSP for low-power energy-efficient embedded systems

This paper presents the design of an asynchronous DSP that is code compatible with the Motorola DSP56000, with the objective of low power and high energy efficiency to extend the lifespan of the batteries in embedded systems embodying the DSP. It features a unified and low-overhead pipeline flush design, a common-case oriented and efficient single-instruction repeating design, and retimed and single-cycle address generation. The asynchronous DSP is implemented using 130 nm CMOS process and is completely standard-cell based. Pre-layout simulation results demonstrate an equivalent speed of 61.5 MIPS and energy dissipation of 54.5 μW/MIPS @ 1.2 V running a Radix 2 FFT benchmark program, and a 30.0% energy reduction compared to the clock-gated synchronous counterpart.

CMOS WTA maximum and minimum circuits with their applications to analog switch and rectifiers

This paper presents design of a voltage-mode multiple-inputs winner-take-all (WTA) maximum (max) and minimum (min) circuits. The proposed circuits are realized in a CMOS technology with low-component counts of transistors. They display usability of the proposed building block, where the maximum bandwidth of voltage follower is around 1GHz and low-delay time is around 1.5ns with high-input and low-output impedances. The THD obtained is around 0.8% within the 0.6Vp−p input range. The power dissipation of the proposed circuits is obtained to be around 0.62mW with ±1.25V power supplies. In applications, half-wave and full-wave rectifiers and analog switch are included. Computer simulation results by using SPICE program with TSMC 0.25μm are carried out to show the performance of the proposed WTA max and min circuits, rectifiers and analog switch. In addition, the sample layout of the max circuit occupies an area of around 798μm2 and post-layout simulation results are exhibited to concrete the pre-layout simulation results.

A cascaded charge-sharing technique for an EDP-efficient match-line design in CAMs

A novel cascaded charge-sharing technique is presented in content-addressable memories (CAMs), which not only effectively reduces the match-line (ML) power by using a pre-select circuit, but also realizes a high search speed. Pre-layout simulation results show a 75.9% energy-delay-product (EDP) reduction of the MLs over the traditional precharge-high ML scheme and 41.3% over the segmented ML method. Based on this technique, a test-chip of 64-word × 144-bit ternary CAM (TCAM) is implemented using a 0.18-μm 1.8-V CMOS process, achieving an 1.0 ns search delay and 4.81 fJ/bit/search for the MLs.

A Current-Recycling Technique for Shadow-Match-Line Sensing in Content-Addressable Memories

A current-recycling technique for shadow-match-line (SML) sensing in content-addressable memories (CAMs) is presented. In order to minimize energy-overhead, a novel current-recycling voltage detector (CRVD) is devised, whose working current is reused to charge up the match-line (ML) to determine matches or mismatches. Furthermore, with this CRVD, the word circuits realize fast-disable of the charging paths in case of mismatches. Since the majority of CAM words are mismatched, a significant power is reduced with a high search speed. Pre-layout simulation results show the proposed 256-word times 144-bit ternary CAM, based on a 0.13-mum 1.2-V CMOS process, achieves 0.51 fJ/bit/search for the word circuit with less than 900-ps search time. The achievement illustrates a 74.2% energy-delay-product (EDP) reduction as compared with the speed-optimized current-saving scheme. Post-layout simulation results of the word circuits show 0.65 fJ/bit/search energy per search with 1.2-ns search time.

Asynchronous arbiter for micro-threaded chip multiprocessors

This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors and its corresponding pre-layout simulation results using VHDL. The arbiter exploits the advantage of a concurrency control instruction (Brk) provided by the micro-threaded microprocessor model to set the priority processor and move the circulated arbitration token to the most likely processor to issue the create instruction. This mechanism provides latency hiding during token circulation by decoupling the micro-threaded processor from the ring's timing. The arbiter provides a very simple arbitration mechanism and can be used for chip multiprocessor arbitration purposes.

Algorithm and architecture for a high density, low power scalar product macrocell

The authors present a design approach for an arithmetic macrocell that computes the scalar product of two vectors, an operation ubiquitously present in the solution of many communications and digital signal processing problems. The core of the proposed architecture is a full combinational design containing a partial product generator, a partial product accumulator and a vector accumulator. The design addresses the competing optimisation goals of VLSI area, power dissipation and latency in the deep submicron regime. Compared with conventional merged arithmetic architectures, the proposed macrocell design represents a substantial improvement in the VLSI layout with little area wastage, a high degree of regularity and a good scalability for different vector lengths and operand widths. A theoretical analysis shows that the design of a 16-bit scalar product multiplier for input vectors with 16 elements, in comparison with traditionally designed architecture, achieves a saving of 38.6% in the silicon area, an up to 73% increase in the area usage efficiency and a 29.4% saving in the interconnect delay. Post-layout simulations of the proposed circuit, based on a 0.18 /spl mu/m CMOS process, show an average power dissipation of 64.96 mW and a latency of 6.92 ns at a standard supply voltage of 1.8 V, a superior performance for a single cycle instruction in a high-speed, low voltage 16-bit digital signal processor operating at 144 MHz. The use of shorter interconnects and more equalised interconnect delays, leads to the power dissipation and delay incurred by the interconnects being substantially reduced. Post-layout simulation of our proposed circuit at supply voltages ranging from 0.7 to 3.3 V shows a significant power reduction of 6 to 13% over the pre-layout simulation results of the conventional design.