Predistortion Linearization Research Articles

Behavioral Modeling and Digital Predistortion for Power Amplifier Based on the Sparse Smooth Twin Support Vector Regression Method

In this paper, a sparse smooth twin support vector regression (Sparse‐STSVR) model for power amplifier (PA) behavioral modeling is obtained by pruning the kernel matrix based on Cholesky decomposition. Based on the primal smooth twin support vector regression (STSVR) model, the Nystrom approximate matrix of the kernel matrix is found to replace the original kernel matrix, thus simplifying the Newton iterative parameter extraction process of the primal STSVR model and accelerating the convergence of the algorithm. In addition, the new rank approximation kernel matrix has the characteristic of sparse parameters, which further reduces the computational complexity of the feedforward link of the digital predistorter. The 100 MHz 5G New Radio (NR) signal is used for verify the effect of PA modeling and digital predistortion (DPD) experiment. The results show that the proposed method can improve the normalized mean square error (NMSE) by about 2 ~ 3 dB with fewer coefficients compared with the previously proposed machine learning model, and the predistortion linearization effect improves by nearly 3 dB on the adjacent channel power ratio (ACPR), which achieves a good trade‐off between model performance and computational complexity. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.

Full-Wave Digital Predistortion Linearization Based on Memory Polynomials for HF Power Amplifiers

Full-Wave Digital Predistortion Linearization Based on Memory Polynomials for HF Power Amplifiers

GPU versus FPGA implementation of a digital predistortion linearizer for wideband radiofrequency power amplifiers

This paper presents and compares the implementation of a digital predistortion (DPD) linearizer for radiofrequency power amplifiers (PAs) considering two different hardware acceleration platforms. Both graphics processing unit (GPU)-based and field programmable gate arrays (FPGA)-based implementations of the DPD are capable to meet the high throughput requirements for linearizing the PA with current 5G new radio (NR) wideband signals. A comparison in terms of hardware resources usage, precision, throughput and linearization performance is provided for both GPU and FPGA implementations of a DPD based on the generalized memory polynomial (GMP) behavioral model.

Digital Predistortion Linearization of a GaN HEMT Push-Pull Power Amplifier for Cable Applications With High Fractional Bandwidth

This paper presents two linearization strategies for a custom-designed wideband push-pull (PP) power amplifier (PA) for wired communication applications such as, for example, cable TV. Two digital predistortion (DPD) behavioral models are proposed to meet the in-band and out-of-band linearity requirements when efficiently amplifying wideband DOCSIS signals with high fractional bandwidth (FBW). A radiofrequency (RF) DPD linearizer based on a band-pass generalized memory polynomial (BP-GMP) behavioral model and a baseband (BB) I-Q DPD linearizer based on a harmonic distortion GMP (HD-GMP) behavioral model are proposed. Both DPD models take into account the harmonic distortion typical of high FBW amplification. Experimental results will show high efficient and linear amplification of a 4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 192 MHz composite DOCSIS signal by properly combining a crest factor reduction (CFR) technique and the proposed DPD strategies.

Signal Reconstruction Deep Residual Neural Network-Based Bandwidth Augmented Methods for DPD Linearization

In this letter, a signal reconstruction deep residual neural network (SRDRNN)-based bandwidth augmented method for digital predistortion (DPD) linearization of a radio frequency (RF) power amplifier (PA) is proposed. The SRDRNN is utilized to interpolate the samples from the analog-to-digital (ADC) converter in the DPD feedback path of the RF PA so as to increase its bandwidth. The experimental results illustrate that the SRDRNN can accurately produce the out-of-band spectrum regrowth of the equivalent baseband signal for a PA. It can also be directly applied to another PA with the same type. Finally, the effectiveness of SRDRNN-based bandwidth augmented method is verified with DPD linearization experiment. Both of the feedback signals reconstructed by the SRDRNN for the training PA and the test PA exhibit an excellent linearization performance.

Digital Linearization of Wideband Envelope Tracking Power Amplifiers for Mobile Terminals

This article presents a low-complexity linearization method to compensate for multisource nonlinear distortion in wideband envelope tracking (ET) power amplifiers (PAs) for 5G new radio (NR) mobile terminals. The proposed linearization approach consists in an envelope leakage cancellation (ELC) system operating in the dynamic supply path and a 2-D digital predistortion (2-D-DPD) linearizer acting on the baseband complex modulated signal. In a first step, an envelope generalized memory polynomial (EGMP) behavioral model is proposed to compensate for the unwanted radio frequency (RF) leakage that appears at the output of ET modulator (ETM). Then, a baseband 2-D-DPD linearizer based on a slow envelope-dependent generalized memory polynomial (SED-GMP) behavioral model is used to further enhance the linearization performance. The proposed method is validated on a system-on-chip (SoC) ET PA board for mobile applications. The reported experimental results show how the proposed digital linearization approach can mitigate the linearity and efficiency trade-off in ET PAs. Consequently, the out-of-band linearity requirement of −36 dBc of adjacent channel power ratio (ACPR) is met for 5G-NR test signals with bandwidths ranging from 60 to 200 MHz at 2.55 GHz (band B41), with an overall ET PA power efficiency ranging from 10.1% and up to 16.5%, depending on the signal bandwidth.

A General Digital Predistortion Linearization Scheme for Hybrid Beamforming System

Hybrid beamforming multiple-input multiple-output (MIMO) system has attracted a lot of attention in recent years since it significantly reduces the hardware cost compared to the fully digital beamforming system. However, with hybrid beamforming, the one-to-one mapping between the radio frequency (RF) chain and the nonlinear power amplifier (PA) is destroyed. The PA nonlinearity cannot be compensated by conventional digital predistortion (DPD) algorithms. In this article, we propose a novel multiple-input DPD model for hybrid beamforming MIMO systems. An extra digital compensation block is introduced in the feedback path. With the feedback compensation block, the proposed DPD can linearize the PA output signal as well as the aggregated far-field signal. What is more, we propose a DPD estimation algorithm with much reduced complexity. Comparing to existing solutions, the proposed scheme achieves satisfactory performance for hybrid beamforming system. It does not rely on the measurement of the channel or the assumption of massive antennas. Simulation results demonstrate the effectiveness of the proposed DPD scheme.

Doherty Power Amplifier With Extended High-Efficiency Range Based on the Utilization of Multiple Output Power Back-Off Parameters

This article presents a novel method of extending the high-efficiency range of Doherty power amplifiers (DPAs) by utilizing multiple output power back-off (OBO) parameters. The OBO extension techniques of the DPAs, such as complex combining load (CCL), virtual stub (VS), and out-phased current combining (OCC) methods, were defined, and a general expression for these OBO extension techniques was derived. Using the general expression, three OBO extension methods were comparatively and comprehensively analyzed. Based on the analysis, the DPA with an extended OBO can be designed by simultaneously employing multiple back-off techniques with a high degree of freedom. To verify the general expression and its analysis, a DPA design for the frequency band of 3.45–3.75 GHz with GaN HEMTs was conducted using multiple OBO extension techniques of VS and OCC methods for a large OBO of 8.5 dB. Using a long-term evolution (LTE) signal with a signal bandwidth of 20 MHz and a peak-to-average power ratio (PAPR) of 8 dB, the drain efficiency (DE) of 38.9%–56.8% was achieved at the average output power levels of 34.4–36.8 dBm while satisfying ACLR of no larger than −45 dBc with digital predistortion (DPD) linearization. Under excitation of a 5G new radio (NR) signal with a signal bandwidth of 100 MHz and a PAPR of 8 dB, the DE of 38.5%–50.2% was achieved at the average output power levels of 34.6–36.8 dBm with an ACLR of under −24.6 dBc without DPD linearization.

A Generic Theory for Design of Efficient Three-Stage Doherty Power Amplifiers

An analytical load—pull-based design methodology for three-stage Doherty power amplifiers (PAs) is presented and demonstrated. A compact output combiner network, together with the input phase delays, is derived directly from transistor load—pull data and the design requirements. The technique opens up a new design space for three-stage Doherty PAs with reconfigurable high-efficiency power back-off levels. The method is designed to enable high transistor power utilization by maintaining full voltage and current swings of the main and auxiliary amplifier cells. Therefore, a wide efficiency enhancement range can be achieved also with symmetrical devices. As a proof of concept, a 2.14-GHz 30-W three-stage Doherty PA with identical gallium nitride (GaN) HEMT active devices is designed, fabricated, and characterized. The prototype PA is able to linearly reproduce 20-MHz long-term evolution signals with 8.5- and 11.5-dB peak-to-average power-ratio (PAPR), providing average efficiencies of 56.6% and 46.8% at an average output power level of 36.8 and 33.8 dBm, respectively. Moreover, an average efficiency as high as 54.5% and an average output power of 36.3 dBm have been measured at an adjacent power leakage ratio of −45.7 dBc for a 100-MHz signal with 8.5 dB of PAPR, after applying digital predistortion linearization.

Reconfigurable DPD Based on ANNs for Wideband Load Modulated Balanced Amplifiers Under Dynamic Operation From 1.8 to 2.4 GHz

This article proposes a methodology to ensure linear amplification of a load modulated balanced amplifier (LMBA) while keeping the power efficiency as high as possible over a frequency band ranging from 1.8 to 2.4 GHz and where the transmitted signals can present different bandwidth (BW) configurations. The proposed reconfigurable linearization methodology consists of, in a first step, tuning some free parameters (with dependence on the signal BW and frequency of operation) of the LMBA to trade-off linearity and power efficiency. In a second step, two multipurpose adaptive digital predistortion (DPD) linearizers are considered, properly combined with crest factor reduction (CFR) techniques, to meet the required linearity specifications. Either a DPD based on artificial neural networks or a DPD based on polynomials can be selected taking into account the compromise between computational complexity and linearization performance. Experimental results will validate the proposed methodology to guarantee the linearity levels (ACPR <−45 dBc and EVM <1%) with high power efficiency in an LMBA under dynamic transmission, where both the signal BW (from 20 and up to 200-MHz instantaneous BW) and frequency of operation (in the range of 1.8–2.4 GHz) change.

A Novel Analog Predistortion Linearizer Based on a Schottky diode for Communication Applications

Background and Objectives: In order to compensate the nonlinearity, several linearization approaches such as feedback, feed-forward, and predistortion have been proposed. Among these linearization methods, the analog predistortion (APD) method is very suitable for the power amplifier and TWTA linearization, because it has a good compromise between complexity, linearity improvement and bandwidth. On the other hand, analog predistortion circuit can be added to existing amplifiers as a separate circuit. Many of the reported linearizer circuits are capable of linearizing power amplifiers with high gain and phase variations. However, these circuits are complex and bulky due to the use of distortion producer, phase shifter, adjustable attenuator, combiner/divider, and control unit. The objective of this paper is increasing the dynamic range of the predistorter by a simple proposed circuit. Hence, linearization capability of the linearizer is boosted.Methods: A new analog predistortion linearizer based on a coupler and a Schottky diode is presented. The proposed structure satisfies linearization requirements of the solid-state power amplifiers (SSPAs) and traveling wave tube amplifiers (TWTAs). Using a parallel combination of two Schottky diodes along with transmission line in port 2 and 3 of the coupler, the dynamic range of reflection coefficient of each port is increased compared to using a single diode in each branch. By increasing the range of reflection signal, the linearization capability has been increased to linearize power amplifiers and TWTAs. The AM/AM and AM/PM of the linearizer is controlled by changing the bias voltage of power supply.Results: The simulation results show that about 30° phase shift and 5 dB gain expansion can be compensated for power amplifiers and TWTAs. Because of utilizing two diodes, the linearization capability of the new linearizer is augmented compared to the conventional linearizer.Conclusion: A novel analog predistortion circuit based on the hybrid coupler and Schottky diodes is presented. The suggested topology increases the dynamic range of reflected power from each port. Using the proposed idea, AM/AM and AM/PM characteristics are expanded such that this characteristic can linearize the power amplifier with high linearity.

A 919 MHz—923 MHz, 21 dBm CMOS Power Amplifier With Bias Modulation Linearization Technique Achieving PAE of 29% for LoRa Application

This paper presents a bias modulation linearization technique for a 919-923MHz CMOS power amplifier which employs driver voltage modulation and main amplifier split bias. Through the proposed linearization technique, it is observed that the peak third-order intercept point (OIP3) across the output power is shifting according to the bias conditions of the split-bias power amplifier (SBPA). The third-order transconductance (gm₃) terms are suppressed at the output by phase cancellation achieved by optimization of the bias voltages of the PA. A high dynamic range bias circuit is integrated at the driver and split main to enhance the linearity of the CMOS PA, eradicating the need for pre-distortion linearizers. The two-stage SBPA is designed and fabricated in a 180 nm CMOS process with six-metal layers and a chip size of 1.820 x 1.771 mm² to operate at the supply voltage of 3.3 V. The bias voltages of both driver and split main stages are varied from 0 V to 2.0 V with a linear step size of 0.2 V. The proposed SBPA delivers a saturated output power (P_out) of 27 dBm with maximum power-added efficiency (PAE) of 44.4 % and peak OIP3 of 39 dBm. A maximum linear P_out of 21 dBm with 29 % PAE is achieved at an adjacent channel leakage ratio (ACLR) of -30 dBc and 4 % error vector magnitude (EVM), satisfying the LoRa specifications.

Hybrid integrated low-noise linear chirp frequency-modulated continuous-wave laser source based on self-injection to an external cavity

A hybrid integrated low-noise linear chirp frequency-modulated continuous-wave (FMCW) laser source with a wide frequency bandwidth is demonstrated. By employing two-dimensional thermal tuning, the laser source shows frequency modulation bandwidth of 10.3 GHz at 100 Hz chirped frequency and 5.6 GHz at 1 kHz chirped frequency. The intrinsic linewidth of 49.9 Hz with 42 GHz continuous frequency tuning bandwidth is measured under static operation. Furthermore, by pre-distortion linearization of the laser source, it can distinguish 3 m length difference at 45 km distance in the fiber length measurement experiment, demonstrating its application potential in ultra-long fiber sensing and FMCW light detection and ranging.

Comparison of Feature Selection Techniques for Power Amplifier Behavioral Modeling and Digital Predistortion Linearization.

The power amplifier (PA) is the most critical subsystem in terms of linearity and power efficiency. Digital predistortion (DPD) is commonly used to mitigate nonlinearities while the PA operates at levels close to saturation, where the device presents its highest power efficiency. Since the DPD is generally based on Volterra series models, its number of coefficients is high, producing ill-conditioned and over-fitted estimations. Recently, a plethora of techniques have been independently proposed for reducing their dimensionality. This paper is devoted to presenting a fair benchmark of the most relevant order reduction techniques present in the literature categorized by the following: (i) greedy pursuits, including Orthogonal Matching Pursuit (OMP), Doubly Orthogonal Matching Pursuit (DOMP), Subspace Pursuit (SP) and Random Forest (RF); (ii) regularization techniques, including ridge regression and least absolute shrinkage and selection operator (LASSO); (iii) heuristic local search methods, including hill climbing (HC) and dynamic model sizing (DMS); and (iv) global probabilistic optimization algorithms, including simulated annealing (SA), genetic algorithms (GA) and adaptive Lipschitz optimization (adaLIPO). The comparison is carried out with modeling and linearization performance and in terms of runtime. The results show that greedy pursuits, particularly the DOMP, provide the best trade-off between execution time and linearization robustness against dimensionality reduction.

Bandwidth‐extended single‐input switchable Doherty power amplifier based on dual compensating reactance with adjusted drain voltage

This study presents a switchable Doherty power amplifier (S-DPA) based on dual compensating reactance and adjusted drain voltage with 124% fractional bandwidth (FBW) using single-input architecture. The proposed S-DPA can be operated in wideband mode (WB-MOD) and dual-band mode (DB-MOD) with a larger power back-off region through one-click switching directly. The needed back-off impedance in both operation modes is achieved by using the dual compensating reactance for bandwidth extension. Meanwhile, a load modulation enhancement technique through adjusting the drain voltage of both the carrier and peaking amplifiers is proposed for proper load modulation in DB-MOD. To verify the proposed techniques, an S-DPA was designed and fabricated. Measurement results show that the proposed S-DPA has an efficiency of 51.3%–70.3% at saturated power of higher than 43.4 dBm over the frequency band of 0.8–3.4 GHz with 124% FBW. The 6-dB back-off efficiency in WB-MOD (1.3–2.9 GHz) is 45.3%–56.1% and the 8-dB back-off efficiency in DB-MOD (0.8–1.3 GHz & 2.9–3.4 GHz) is 41.6%–57.9%. 80-MHz modulated signals with 6.2-dB and 8.2-dB peak to average power ratios are used to evaluate the modulated signal performance in two modes. The DPA can achieve an average efficiency of up to 56% with high linearity after digital pre-distortion linearisation.

A 28GHz Power Amplifier with Analog Predistortion Linearizer in 65nm CMOS

This paper proposes that a radio frequency power amplifier is suitable for a 5G millimeter wave. It adopts a three-stage single-ended structure at 28GHz. An analog predistortion linearization method is used to improve the linearity of the power amplifier (PA). As a result, there is a significant improvement in power-added efficiency (PAE) and linearity is achieved. The Ka-band PA is implemented in TSMC 65nm CMOS process. At 1.2V supply voltage, the PA proposed in this paper achieves a saturated output power of 15.9dBm and a PAE of 16%. After linearization, the output power at the 1dB compression point is increased by 2dBm, with efficient gain compensation performance.

Machine-Learning Assisted Optimisation of Free-Parameters of a Dual-Input Power Amplifier for Wideband Applications.

This paper presents an auto-tuning approach for dual-input power amplifiers using a combination of global optimisation search algorithms and adaptive linearisation in the optimisation of a multiple-input power amplifier. The objective is to exploit the extra degrees of freedom provided by dual-input topologies to enhance the power efficiency figures along wide signal bandwidths and high peak-to-average power ratio values, while being compliant with the linearity requirements. By using heuristic search global optimisation algorithms, such as the simulated annealing or the adaptive Lipschitz Optimisation, it is possible to find the best parameter configuration for PA biasing, signal calibration, and digital predistortion linearisation to help mitigating the inherent trade-off between linearity and power efficiency. Experimental results using a load-modulated balanced amplifier as device-under-test showed that after properly tuning the selected free-parameters it was possible to maximise the power efficiency when considering long-term evolution signals with different bandwidths. For example, a carrier aggregated a long-term evolution signal with up to 200 MHz instantaneous bandwidth and a peak-to-average power ratio greater than 10 dB, and was amplified with a mean output power around 33 dBm and 22.2% of mean power efficiency while meeting the in-band (error vector magnitude lower than 1%) and out-of-band (adjacent channel leakage ratio lower than −45 dBc) linearity requirements.

Digitally-Compensated Wideband 60 GHz Test-Bed for Power Amplifier Predistortion Experiments.

Millimeter waves will play an important role in communication systems in the near future. On the one hand, the bandwidths available at millimeter-wave frequencies allow for elevated data rates, but on the other hand, the wide bandwidth accentuates the effects of wireless front-end impairments on transmitted waveforms and makes their compensation more difficult. Research into front-end impairment compensation in millimeter-wave frequency bands is currently being carried out, mainly using expensive laboratory setups consisting of universal signal generators, spectral analyzers and high-speed oscilloscopes. This paper presents a detailed description of an in-house built MATLAB-controlled 60 GHz measurement test-bed developed using relatively inexpensive hardware components that are available on the market and equipped with digital compensation for the most critical front-end impairments, including the digital predistortion of the power amplifier. It also demonstrates the potential of digital predistortion linearization on two distinct 60 GHz power amplifiers: one integrated in a direct-conversion transceiver and an external one with 24 dBm output power.

A Committee Machine Neural Network for Dynamic and its Inverse Modeling of Distortions and Impairments in Wireless Transmitters

The tradeoff between bandwidth efficiency and power efficiency with nonlinear distortion introduced by high power amplifier (HPA) in a modern communication system, at a high bit rate has become a prominent problem. Digital predistortion (DPD), the most cost-effective and yet lesser complex method is a widely used linearization method. In this method, the dynamic nonlinear characteristics of the PA are used to obtain an inverse transfer function to abolish the nonlinearity. The development of a good DPD technique depends on its ability to model an accurate PA behavior and its inverse behavior. Recently, several neural network-based predistortion linearizers had been proposed, and these linearizers are effectively proving their worth, but these methods report inadequate generalization performance in the presence of system imperfections like DC offset, IQ imbalance, and both. The present paper proposes a Mixture of Experts (MOE) based committee machine neural network for modeling the PA/transmitter system transfer function and its inverse transfer function under different system conditions. MOE models encompass a family of modular neural network architectures having several experts network and a single gating network, and targeting to divide a complex problem into simple subtasks. An algorithm based on a maximum likelihood criterion is considered for the MOE network training. The results obtained with the proposed model show good generalization performance with nonlinear HPA and with memory effect in the presence of system imperfections.

Time-Domain Characterization and Linearization of a Dual-Input Power Amplifier Using a Vector Network Analyzer as the Receiver

A newly calibrated testbed based on a commercial vector network analyzer (VNA) is proposed for the fast in-band vector signal characterization and linearization of nonlinear multiport devices. The testbed can acquire both CW and wideband modulated periodic signals without breaking contact with the DUT, in up to five channels. The time-domain measurements are made possible by calibrating all the receivers in the frequency domain. This calibration provides a phase and amplitude correction for the modulation tones of all the incident and reflected waves in the acquisition bandwidth. The measurement bandwidth is determined at calibration by the bandwidth of the periodic OFDM signals used as a phase standard. It is independent of the VNA receivers' bandwidth. A 500-MHz 100 000-tones 64-QAM OFDM constellation is recovered with 0.48% error vector magnitude (EVM). As an application, a dual-input hybrid Doherty-outphasing power amplifier (HD-OPA) is characterized at 2.08 GHz. A CW signal is used to determine the outphasing angle and input power levels, which provides the best drain and power-added efficiencies for each output power. The dynamic response of the dual-input HD-OPA is acquired on five channels by using the same testbed. Various periodic OFDM signals, with 24 000 tones, are measured before and after predistortion linearization in a fraction of a second.