Power Supply Voltage Variations Research Articles

Hardware-in-the-Loop Emulation of a SEPIC Multiplier Converter in a Photovoltaic System

This article presents the development and execution of a Single-Ended Primary-Inductor Converter (SEPIC) multiplier within a Hardware-in-the-Loop (HIL) emulation environment tailored for photovoltaic (PV) applications. Utilizing the advanced capabilities of the dSPACE 1104 platform, this work establishes a dynamic data exchange mechanism between a variable voltage power supply and the SEPIC multiplier converter, enhancing the efficiency of solar energy harnessing. The proposed emulation model was crafted to simulate real-world solar energy capture, facilitating the evaluation of control strategies under laboratory conditions. By emulating realistic operational scenarios, this approach significantly accelerates the innovation cycle for PV system technologies, enabling faster validation and refinement of emerging solutions. The SEPIC multiplier converter is a new topology based on the traditional SEPIC with the capability of producing a larger output voltage in a scalable manner. This initiative sets a new benchmark for conducting PV system research, offering a blend of precision and flexibility in testing supervisory strategies, thereby streamlining the path toward technological advancements in solar energy utilization.

Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages

This work presents an improved input–output (IO) buffer model for signal and power integrity simulation, including power/ground supply voltage (PGSV) variations for the buffer’s input and output stages. Both stages are mathematically modeled from a formulation that is derived from nonlinear electrical circuit analysis, an important aspect that grants these models a good level of generality and, simultaneously, high accuracy. The proposed IO buffer model is linear in the parameters and, therefore, extractable through the linear least-squares technique from the signals acquired in an IO buffer characterization setup. Several validation scenarios, supported on two CMOS driver’s transistor technologies, are performed to evaluate the accuracy of the proposed model. In addition, a comparative analysis is provided, confronting the proposed model’s performance against that of the input/output buffer information specification (IBIS) model, evidencing an outstanding modeling improvement provided by the proposed model.

Characterization of electrically stressed power device metallization using nano-CT imaging

Power devices for automotive products are exposed to higher temperatures, currents, and voltages than common semiconductors. These devices are subject to large variations in the nominal power supply voltage. Power-Temperature Cycling (PTC) is an important reliability stress for power semiconductor devices, which addresses these specific load scenarios. It is known that PTC fails especially occur in the metallization of these power devices. Recent nano-CT imaging methods provide high-resolution 3D measurements on the relevant size scale suitable to spatially analyze these faults in detail. In this work, we demonstrate the suitability of the investigation method based on the study of various via-chain test structures previously stressed in the PTC and visually show the various defects that occurred in the process.

Assessing the accuracy of electronic portal imaging device (EPID)-based dosimetry: I. Quantities influencing long-term stability.

The aim of this study is to reduce the uncertainty associated with determining dose-to-water using an amorphous silicon electronic portal imaging detector (EPID) under reference conditions by identifying and accounting for operational and environmental factors influencing the long-term stability of EPID response. Measurements of the EPID relative response, corrected for variations in linear accelerator (linac) output, were performed regularly over a period of 12 months. For every acquired image set, measurements of detector supply voltages, internal operating temperature, and ambient environmental conditions were obtained. Pearson r correlation coefficients were then calculated for each pair of variables, a subset of which were fitted using multiple linear regression to develop a predictive model of EPID response. Principal component analysis was performed on the dataset to reveal the internal structure of the data in a way that best accounts for the observed variations. The +5.5V power supply voltage, internal operating temperature, and the accumulated dose absorbed in EPID were identified as having the greatest influence on the long-term stability of EPID response. By correcting for the combined effect of these variables, the mean difference in linac output as measured by the EPID relative to a reference class chamber improved from -0.46% to 0.23% over the period of the study. This work suggests that the stability of an EPID over a period of a year can be improved by a factor of two by monitoring and accounting for the effects of variations in power supply voltage, internal temperature of the detector, and accumulated absorbed dose.

Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations.

This paper presents a neural-network based nonlinear behavioral modelling of I/O buffer that accounts for timing distortion introduced by nonlinear switching behavior of the predriver electrical circuit under power and ground supply voltage (PGSV) variations. Model structure and I/O device characterization along with extraction procedure were described. The last stage of the I/O buffer is modelled as nonlinear current-voltage (I-V) and capacitance voltage (C-V) functions capturing the nonlinear dynamic impedances of the pull-up and pull-down transistors. The mathematical model structure of the predriver was derived from the analysis of the large-signal electrical circuit switching behavior. Accordingly, a generic and surrogate multilayer neural network (NN) structure was considered in this work. Timing series data which reflects the nonlinear switching behavior of the multistage predriver’s circuit PGSV variations, were used to train the NN model. The proposed model was implemented in the time-domain solver and validated against the reference transistor level (TL) model and the state-of-the-art input-output buffer information specification (IBIS) behavioral model under different scenarios. The analysis of jitter was performed using the eye diagrams plotted at different metrics values.

CNTFET Circuit-Based Wide Fan-In Domino Logic for Low Power Applications

Carbon nanotube field effect transistors (CNTFETs) are the best alternative option for the metal oxide semiconductor field effect transistor (MOSFET) in the ultra-deep submicron (ultra-DSM) regime. CNTFET has numerous benefits such as lower off-state current, high current density, low bias potential and better transport property as compared to MOSFET. A rolled graphene sheet-based cylindrical tube is constructed in the channel region of the CNTFET structure. In this paper, an improved domino logic (IDL) configuration is proposed for domino logic circuits to improve the different performance metrics. An extensive comparative simulation analysis is provided for the different performance metrics for different circuits to verify the novelty of the proposed IDL approach. The IDL approach saves the leakage power dissipation by 95.61% and enhances the speed by 87.10% for the 4-bit full adder circuit as compared to the best reported available domino method. The effects of the number of carbon nanotubes (CNTs), temperature, and power supply voltage variations are estimated for leakage power dissipation for the 16-input OR (OR16) gate. The reliability of different performance metrics for different circuit is calculated in terms of uncertainty by running the Monte Carlo simulations for 500 samples. Stanford University’s 32[Formula: see text]nm CNTFET model is applied for circuit simulations.

Newly energy-efficient SRAM bit-cell using GAA CNT-GDI method with asymmetrical write and built-in read-assist schemes for QR code-based multimedia applications

The novel design of asymmetric single-ended ten-transistor SRAM bit-cell (SE 10T-SRAM) using gate-all-around (GAA) carbon nanotube (CNT) FETs-based GAA CNT-GDI method along with dual-chirality technique for CNTs, the asymmetric write-assist and built-in read-assist schemes in the presence of more saving area and less energy consumption is suggested for portable/mobile multimedia applications. Based on the analytical-compact model, an equation for calculating write-static margin (WSNM) is presented by expressing the degree of dependence of the metric on the power supply voltage variation for the suggested bit-cell structure. The results of extensive simulations to evaluate the proposed bit-cell in single and multi-array structures indicate better static/dynamic noise margins, less sensitivity to process, voltage and temperature (PVT) variations, improvement of basic parameters in the presence of contact length changes, more noise-immunity with scalability at cell supply voltage, and better results in other comprehensive figure of merits (FoMs) parameter compared to nanotechnology-based counterpart circuits with the same number of transistors in the 16 nm technology node. Also, evaluating the proposed structure in the presence of changes in the contact length parameter of other transistors as a contact length sizing-level solution, indicating the achievement of an improved structure in the basic parameters such as static noise margin, power consumption, and energy-delay product (EDP) parameter compared to the default structure with a minimum-sizing contact length. Finally, in order to use the proposed bit-cell in a real application, the suggested structure for storing images based on quick response (QR) code is examined with a link between MATLAB and synopsys H-SPICE simulator tools based on suggested algorithm. The results demonstrate that the suggested bit-cell is with more appropriate and significant results in terms of comprehensive FoMs, in which the evaluations concerning the appropriate accuracy in pixel-by-pixel storage of images based on the peak signal-to-noise ratio (PSNR) and the mean structural similarity index measure (MSSIM) metrics, compared to other well-known counterpart schemes confirms the superiority of the proposed design. Hence, the proposed design can be used for various areas regarding multimedia device applications.

Transistor Width Effect on the Power Supply Voltage Dependence of α-SER in CMOS 6T SRAM

We present the experimental results on the impact of transistor width modulation and power supply voltage variation on the $\alpha $ -soft error rate (SER) in a 65-nm CMOS 6T static random access memory (SRAM) obtained from an accelerated test experiment using an Am- $241~\alpha $ -source. Five 6T cells with various combinations of transistor widths were tested and the results show that nMOS and pMOS widths play a different role on SER. We also found that the transistor width modulation effectiveness is highly dependent on the power supply voltage. In particular, the results show that at around nominal voltages, widening all pMOS while keeping all nMOS minimum sized, is the best way to improve SER. However, at lower voltages the results become completely different, and the best option for an overall SER improvement is to keep all transistors minimum sized.

EXPERIMENTAL STUDY AND ANALYSIS OF WOUNDED TYPE D.C. MOTOR WITH VARIABLE POWER SUPPLY

In this paper we are observed about maximum R.P.M. , in this way we are used the Wounded type D.C. Motor with Variable Voltage Power Supply and 1Amp.,2Amp., 3Amp. For the purpose of the finding of the variable voltages we are used the voltages regulator. The Wounded type D.C. Motor are used in various industrial application.

A wide tuning range VCO design using multi-pass loop complementary current control with IMOS varactor for low power applications

In this work a wide-bandwidth low-power voltage-controlled oscillator (VCO) design is presented using a new differential delay cell with complementary current control mechanism and inversion mode MOSFET (IMOS) varactor. The variations in output oscillation frequency of the VCO has been achieved by changing the capacitance of the delay cell with the usage of IMOS varactor containing two PMOS transistors connected in parallel. The proposed three-stage VCO has been designed with 1.8 V power supply in 180 nm CMOS technology. Capacitance of IMOS varactor has been varied by altering the source/drain voltage Vcontrol and back-gate voltage Vsb of IMOS. The variations in power supply voltage from 1 V to 2.4 V provides output frequency from 1.893 GHz to 7.926 GHz with power dissipation of 0.953 mW to 24.261 mW with IMOS varactor width of 5 µm. The results have been extended for the IMOS width of 10 µm, 15 µm and 20 µm. The tuning range of 122% has been achieved with the power supply tuning method. The variations in source/drain voltage of IMOS from 1 V to 2.4 V provides the output frequency from 6.373 GHz to 5.460 GHz with power dissipation of 9.62 mW. The tuning range of 15.7%, 22.3%, 44% and 40.6% has been obtained for IMOS with widths of 5 μm, 10 μm, 15 μm and 20 μm with the source/drain voltage Vcontrol variations. Further, frequency variation from 5.895 GHz to 6.406 GHz has been obtained with back-gate voltage Vsb tuning of IMOS varactor from 0 V to 2.4 V. The phase noise measured for the VCO is −90.67 dBc/Hz@1 MHz and the figure of merit (FoM) for the VCO is 172.86 dBc/Hz with supply voltage of 1.8 V. Proposed VCO circuit achieved a low power dissipation, wide tuning range, better phase noise and figure of merit (FoM).

A low power VCO design using composite load for delay cell with IMOS varactor for wider tuning range

In this paper, a new low-power voltage-controlled oscillator (VCO) design is presented using inductive composite load for the delay cell and inversion mode MOSFET (IMOS) varactor using 180nm CMOS technology. The output oscillation frequency of the VCO has been changed by varying the capacitance of the delay cell with the usage of IMOS varactor comprising two PMOS transistors connected in parallel. Variation in source/drain voltage (Vct) and back-gate voltage (Vsb) of IMOS changes the capacitance of IMOS resulting in variations in output oscillation frequency of VCO. Power supply voltage (Vdd) variations from 1V to 2. 4V gives output oscillation frequency from 0. 972 GHz to 4. 231 GHz and consumes power from 0. 002mW to 0. 919mW with IMOS varactor width of 2µm. The results have been drawn out for the IMOS width of 5µm, 8µm and 12µm. The source/drain voltage (Vct) variation of IMOS from 1V to 2. 4V show the output oscillation frequency from 2. 648 GHz to 3. 253 GHz and achieves power consumption of 0. 279mW. Results have been further extended for IMOS with widths of 2μm, 5μm, 8μm and 12μm and a tuning range of 21% has been obtained for source/drain voltage (Vct) variations. Further, the back-gate voltage (Vsb) tuning of IMOS varactor from 1V to 2. 4V shows frequency variations from 3. 114 GHz to 3. 282 GHz. The VCO shows a phase noise of-107. 77dBc/Hz@1MHz offset from centre frequency and the figure of merit (FoM) for the VCO is -168. 94dBc/Hz with supply voltage of 1. 8V. Proposed VCO tunes the output frequency with IMOS varactor loading without changing the overall power dissipation of circuit. Proposed VCO circuit achieved a low power dissipation, wide tuning range, better phase noise and figure of merit (FoM).

Clock Jitter Reduction and Flat Frequency Generation in PLL Using Autogenerated Control Feedback

In this paper, a method has been proposed by which one can reduce the clock jitter and achieve almost flat frequency clock output from the phase-locked loop (PLL), independent of the power supply voltage fluctuation. These voltage fluctuations occur when a given chip comes out from the sleep mode to the active mode. This causes the chip to draw a hasty current, which in turn produces LdI/dt noise. That causes the voltage to drop and also to oscillate at the power delivery network’s resonance frequency. This power supply noise causes clock jitter. The voltage-controlled oscillator of the proposed PLL is designed at 45-nm technology such that when there is supply voltage variation, it is automatically corrected by a feedback methodology having only 11-ps response time delay, compared to 588-ps clock period. Simulation result shows that, for the proposed new PLL design, the number of places where the clock periods are altered due to this power supply voltage fluctuation is reduced. The performance of the proposed PLL design in terms of reduction of clock jitter, caused by the variation of power supply voltage and the flatness of the frequency versus power supply voltages, is tested by feeding the clock to a circuit (c17 of ISCAS’85) for the conventional methodology and also for our new methodology. It has been shown that, using the proposed method, the clock jitter caused by the power supply noise can be reduced by about 50% compared to the conventional design methodology.

Simplified topology for integrated circuit buffer behavioural models

This paper addresses the behavioural modelling of digital integrated circuit buffers for performance assessment of high-speed data links. A new modelling technique, with several important advantages is described. All the requirements of black-box identification are met: the approach relies exclusively on the observation of the external port voltages and currents, thus allowing the extraction of models that mimic the operation of real devices without insight on their internal structure. Furthermore, unlike the standard algorithms currently used in EDA tools, the method described in this study provides a straightforward solution to modelling the input-output behaviour. Good model performance in overclocking conditions is an important advantage. This study also investigates the possibility of accounting for power-supply voltage variations and provides a simple solution.

Investigation of light doping and hetero gate dielectric carbon nanotube tunneling field-effect transistor for improved device and circuit-level performance

We perform a comparative study (both for device and circuit simulations) of three carbon nanotube tunneling field-effect transistor (CNT-TFET) designs: high-K gate dielectric TFETs (HK-TFETs), hetero gate dielectric TFETs (HTFETs) and a novel CNT-TFET-based combination of light doping and hetero gate dielectric TFETs (LD-HTFETs). At device level, the effects of channel and gate dielectric engineering on the switching and high-frequency characteristics for CNT-TFET have been theoretically investigated using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green’s functions solved self-consistently with Poisson’s equations. It is revealed that the proposed LD-HTFET structure can significantly reduce leakage current, enhance control ability of the gate on the channel, improve the switching speed, and is more suitable for use in low-power, high-frequency circuits. At circuit level, using HSPICE with look-up table-based Verilog-A models, the performance and reliability of CNT-TFET logic gate circuits is evaluated on the basis of power consumption, average delay, stability, energy consumption and power-delay product (PDP). Simulation results indicate that, compared to a traditional CNT-TFET-based circuit, the one based on LD-HTFET has a significantly better performance (static noise margin, energy, delay, PDP). It is also observed that our proposed design exhibits better robustness under different operational conditions by considering power supply voltage and temperature variations. Our results may be useful for designing and optimizing CNTFET devices and circuits.

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

ABSTRACTThis paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit’s delay, power and power–delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

CMOS ring oscillator with combined delay stages

Full transistor voltage control oscillators by delay stages are studied in this paper. First we describe the general conditions of oscillators and after introducing some common inverters, calculating their delay times, we analyze the dependence of delay time to variation of power supply voltage. The analyzing results show that the delay of basic type inverter varies in the opposite direction as that of current starved inverter, therefore to achieve better frequency stability versus voltage power supply changing, some combined structures of inverters are presented. The results of simulation by 0.18 CMOS technology library of HSPICE approve the analysis results.

Skew violation verification in digital interconnect signals based on signal addition

Signal integrity perturbations are unavoidable in current high performance circuits implemented in nanometer technologies. In this paper, a novel methodology based on the signal addition of two digital signals to verify skew violations is proposed. This methodology allows the implementation of a compact sensor for on-chip verification of the skew in digital interconnect signals. The monitor is implemented in a commercial CMOS 65 nm technology. The compact size of the monitor allows its use for verifying several internal nodes with low area penalty. The impact of process, power supply voltage and temperature variations (PVT) on monitor resolution is analyzed. Simulation results show that the monitor is effective for identifying abnormal skews due to signal integrity issues.

A Smart and Distributed Measurement System to Acquire and Analyze Mechanical Motion Parameters

Abstract This paper presents a low-cost and smart measurement system to acquire and analyze mechanical motion parameters. The measurement system integrates several measuring nodes that include one or more triaxial accelerometers, a temperature sensor, a data acquisition unit and a wireless communication unit. Particular attention was dedicated to measurement system accuracy and compensation of measurement errors caused by power supply voltage variations, by temperature variations and by accelerometers’ misalignments. Mathematical relationships for error compensation were derived and software routines for measurement system configuration, data acquisition, data processing, and self-testing purposes were developed. The paper includes several simulation and experimental results obtained from an assembled prototype based on a crank-piston mechanism

False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation

Static random access memory (SRAM) cores exhibit susceptibility against power supply voltage variation. False operation is investigated among SRAM cells under sinusoidal voltage variation on power lines introduced by direct RF power injection. A standard SRAM core of 16 kbyte in a 90 nm 1.5 V technology is diagnosed with built-in self test and on-die noise monitor techniques. The sensitivity of bit error rate is shown to be high against the frequency of injected voltage variation, while it is not greatly influenced by the difference in frequency and phase against SRAM clocking. It is also observed that the distribution of false bits is substantially random in a cell array.