Power Supply Rejection Ratio Bandgap Research Articles

A high PSRR bandgap voltage reference with piecewise compensation

This paper describes an alternative high power supply rejection ratio (PSRR) bandgap voltage reference (BGR) circuit with piecewise compensation. A proportional to absolute temperature (PTAT) current structure with high loop gain is adopted to achieve high PSRR, a current proportional to absolute temperature square (PTAT2) circuit is used to implement the temperature piecewise compensate. Experimental results of the proposed BGR implemented in a 0.5 ​μm CMOS process demonstrate that a PSRR of 83 ​dB is achieved, and a temperature coefficient (TC) of 8.83 ​ppm/°C over a temperature range of 165 ​°C (−40 ​°C–125 ​°C) is realized.

A 20 ppm/°C Temperature Coefficient and High Power Supply Rejection Ratio Bandgap Reference Implemented in 90 nm CMOS Technology for Low Drop-Out Voltage Regulator Applications

A 20 ppm/°C Temperature Coefficient and High Power Supply Rejection Ratio Bandgap Reference Implemented in 90 nm CMOS Technology for Low Drop-Out Voltage Regulator Applications

Highly accurate capacitor‐free LDO with sub‐1 V −120 dB PSRR bandgap voltage reference

A low dropout (LDO) voltage regulator operated at 5 V power supply, along with a bandgap reference (BGR) voltage circuit with high power-supply rejection ratio (PSRR) is introduced. In the suggested LDO circuit, a low-pass filter for creating a common gate to transmit supply voltage to the power transistor gate is used. During deployment of the RC filter, an artificial resistor with a value of infinity is utilised, which in addition to reduce the chip occupied area, improves the performance of the low-pass filter at frequencies close to DC, and thus improves the PSRR at these frequencies. In addition, the high PSRR of the circuit is mediated by a low-voltage current mode regulator at the heart of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage ( V reg ) for BGR core and op-amp rather than the V DD . These current mirrors reduce the impact of supply voltage variations. The circuit topology is discussed and simulation results are provided. The LDO is also stable without an output capacitor.