Power-supply Noise Attenuation Research Articles

A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO

This brief presents an all-digital PLL (AD-PLL) for a DDR5 registering clock driver (RCD) with a self-biased supply-noise-compensation (SNC) technique. By combining two Nagata current sources that have opposite dependency on supply variations, it offers a constant current to a ring oscillator over a wide range of supply voltage. Thereby, the dynamic voltage droop due to variations in workload is compensated while a voltage margin for mass production is improved. Since the SNC technique operates independently of the PLL loop bandwidth without using feedback, the proposed AD-PLL is free from the stability problem associated with bandwidth overlapping. Quantitative analyses on static and dynamic characteristics of the proposed SNC technique and relevant design considerations are addressed. Fabricated in the 28-nm CMOS technology, the AD-PLL occupies an active area of 0.06 mm2 and consumes 12.1 mW at 3.0 GHz with a 1.1 V supply voltage. The power-supply-noise-attenuation (PSNA) is measured as 40 dB and the integrated rms jitter of 271 fs is observed.

A Resistorless Low-Power Voltage Reference Based on Mutual Temperature Cancellation of VT and VTH

In this paper, a novel resistorless CMOS voltage reference with a sub-one-volt power supply is proposed and simulated in 90 nm CMOS technology. The thermal voltage obtained from ∆VBE is converted into a current (I) proportional to the square of temperature (T2) using a deep triode MOSFET as a resistor. A linear positive temperature coefficient part of the circuit is built by applying this current through a diode-connected MOSFET. VTH is also used as a negative temperature coefficient part. The reference voltage is obtained from the proper combination of these two parts. The proposed circuit is designed in the sub-threshold region to reduce power consumption. Moreover, using bulk biasing and an array of MOSFETs, a trimming circuit is adopted to compensate for the process-related reference voltage variation. The nominal output voltage reference is about 0.5 V with a temperature coefficient of 25.4 ppm/oC over a temperature range of 0 oC to 100 oC. The power supply noise attenuation of 87.5 dB is achieved without any filtering capacitor below 23 Hz at 1 V of Vdd.

Sub 1-V supply voltage-reference based on mutual temperature cancellation of VT and VTH

In this paper, a novel non-bandgap CMOS voltage reference with sub one-volt power supply is proposed and simulated in 0.18 μm standard CMOS technology. Thermal voltage obtained from ∆VBE with positive and threshold voltage of a nMOS transistor with negative temperature coefficient are utilized to achieve a stable-temperature voltage reference. A current proportional-to- threshold voltage and a current proportional-to-absolute-temperature are used to produce positive and negative temperature coefficient parts. The reference voltage is obtained from the proper combination of these two parts. The nominal output voltage reference is about 0.5-V with the temperature coefficient of 36 ppm/ °C across a temperature range of 0–120 °C at 0.9-V of supply. The power supply noise attenuation of 84 dB is achieved without any filtering capacitor below 15 Hz at 1-V of Vdd.

A Resistorless High-Precision Compensated CMOS Bandgap Voltage Reference

A resistorless high-precision compensated CMOS bandgap voltage reference (BGR), which is compatible with a standard CMOS process, is presented in this paper. A higher-order curvature correction method called base-emitter voltage linearization is adapted to directly compensate the thermal nonlinearity of base–emitter voltage. With proper mathematical operations of high-order temperature currents, most of the nonlinear temperature terms in $V_{\mathrm {BE}}$ can be greatly eliminated. The proposed BGR, which is implemented in 0.35- $\mu \text{m}$ CMOS technology, is capable of working down to 2 V supply voltages with 1.14055 V mean output voltage. A minimum temperature coefficient of 1.01 ppm/°C with a temperature range from −40 °C to 125 °C is realized, and a power-supply noise attenuation of 61 dB is achieved without any filter capacitors. The line regulation is better than 2 mV/V from 2 V to 5 V supply voltage while dissipating a maximum supply current of $33~\mu \text{A}$ . The active area of the presented BGR is 180 $\mu \text {m}\times 220\,\,\mu \text{m}$ .

A High-Precision Resistor-Less CMOS Compensated Bandgap Reference Based on Successive Voltage-Step Compensation

A curvature-compensated resistor-less bandgap reference (BGR), which is fabricated in 0.5- $\mu \text{m}$ CMOS process, is proposed in this paper. The BGR utilizes successive voltage-step compensation to produce a temperature-insensitive voltage reference (VR), including one $\Delta V_{\text {GS}}$ step for first-order compensation and another one for higher order curvature correction. Moreover, a supply noise bypassing technique is adopted to achieve good power supply rejection performance up to high frequency. Experimental results demonstrate that this BGR is able to produce a VR of 1.196 V with a temperature coefficient of 3.98 ppm/°C at 3.6-V supply voltage. A power-supply noise attenuation of −84 dB@100 Hz and −37 dB@100 kHz are easily achieved, and the line regulation is better than 0.19 mV/V when supply voltage varies from 2.1 to 5 V. The proposed reference occupies an active area of $356 \,\,\mu \text {m} \times 150 \,\,\mu \text{m}$ and consumes a quiescent current of $38~\mu \text{A}$ .

A Resistorless Low-Power Voltage Reference

A novel low-power temperature-stable voltage reference without resistors is presented in this brief, which is compatible with standard CMOS technology. In order to reduce the temperature nonlinearity in the proposed voltage reference, threshold voltage and a proportional-to-absolute-temperature voltage form the basic linear-temperature components, which are achieved by resistorless threshold voltage extractor and asymmetric differential difference amplifier. Moreover, a self-biased current source with feedback is used to provide stable bias currents for the whole voltage reference, which can improve the power-supply noise attenuation (PSNA) with reduced current mirror errors. Verification results of the proposed voltage reference implemented with 0.18- $\mu\text{m}$ CMOS technology demonstrate that the temperature coefficient of 14.1 ppm/°C with a temperature range of −20 °C to 80 °C is obtained at 1.35-V power supply, and a PSNA of 75.7 dB is achieved without any filtering capacitor while dissipating a maximum supply current of 880 nA. The active area is $115 \mu\text{m}\times 130 \mu\text{m}$ .

A Resistorless CMOS Voltage Reference Based on Mutual Compensation of $V_{T}$ and $V_{\rm TH}$

A novel temperature-stable nonbandgap voltage reference without resistors is presented in this brief, which is compatible with standard digital CMOS technology. Two linear-temperature terms, i.e., thermal voltage VT and threshold voltage VTH, are utilized to realize a low-temperature-dependent voltage reference with a significant reduction of nonlinear temperature terms. A self-biased threshold-voltage extractor circuit without any resistor is used to obtain the VTH and bias currents of the whole circuit. Based on ratioed transistors biased in a strong inversion region and the inverse-function technique, a temperature-insensitive gain can be applied to the proportional-to-absolute temperature term in the reference, and a weighted sum of VT and VTH is achieved. Experimental results of the proposed voltage reference implemented with a 0.35- μm CMOS process demonstrate that the output of voltage reference is 905.5 mV, a temperature coefficient of 14.8 ppm/°C with a temperature range of 0°C-100 °C is obtained at a 3.3-V power supply, and a power-supply noise attenuation of 61 dB is achieved without any filtering capacitor while dissipating a maximum supply current of 65 μA. The active area is 100 μm ×100 μm.

A CMOS Voltage Reference Based on Mutual Compensation of Vtn and Vtp

A novel temperature-stable nonbandgap voltage reference, which is compatible with standard CMOS technology, is presented in this brief. No diodes or parasitic bipolar transistors are used. Based on mutual temperature compensation of the threshold voltages of nMOS and pMOS transistors, a temperature-insensitive voltage reference with significant reduction in temperature dependence of mobility is achieved without using subthreshold characteristics. The problem of a fixed voltage reference value is also avoided by different parameter design. Experimental results of the proposed voltage reference implemented with a 0.35-μm CMOS process demonstrate that the output of the voltage reference is 847.5 mV, a temperature coefficient of 11.8 ppm/ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C with a temperature range from 0 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C to 130 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C is obtained at 3-V power supply, a power-supply noise attenuation of 72 dB is achieved without any filtering capacitor, and the line regulation is better than 0.185 mV/V from 1.8-V to 4.5-V supply voltage dissipating a maximum supply current of 8 μA. The active area of the presented voltage reference is 90 μm ×120 μm.

A 1.6-V 25-$\mu$A 5-ppm/$^{\circ}$C Curvature-Compensated Bandgap Reference

A high precision high-order curvature-compensated bandgap reference (BGR) compatible with standard BiCMOS process is presented in this paper that is capable of working down to input voltages of 1.6 V with 1.285 V output voltage. High-order curvature correction for this reference is accomplished by a novel piecewise technique, which realizes exponential curvature compensation in temperature range, and a logarithmic compensation term proportional to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> In T in higher temperature range through simple structures. Experimental results of the proposed BGR implemented in 0.5-μm BiCMOS process demonstrate that a temperature coefficient (TC) of 5 ppm/°C is realized at 3.6 V power supply, a power-supply noise attenuation (PSNA) of 70 dB is achieved without filtering capacitors, and the line regulation is better than 0.47 mV/V from 1.6 V to 5 V supply voltage while dissipating a maximum supply current of 25 μA. The active area of the presented BGR is 180 μm × 220 μm.

A detailed analysis of power-supply noise attenuation in bandgap voltage references

This paper discusses the power-supply noise attenuation (PSNA) in the frequency domain of four kinds of bandgap voltage reference that represent the basis of typical voltage references. This performance parameter becomes a fundamental design criterion in high-frequency applications where, due to the reduction in the loop gain, spurious signals coming from the power supply cannot be adequately rejected. Precise and simple models, useful for pencil and paper analysis are hereby developed for the four analyzed topologies and, where possible, compensation techniques are discussed. Moreover, the four topologies are compared in detail highlighting both their main features and drawbacks.