Power Semiconductor Industry Research Articles

Correlative, ML-based and non-destructive 3D-analysis of intergranular fatigue cracking in SAC305-Bi solder balls

Reliable connections of electrical components embody a crucial topic in the microelectronics and power semiconductor industry. This study utilises 3D non-destructive X-ray tomography and specifically developed machine learning (ML-) algorithms to statistically investigate crack initiation and propagation in SAC305-Bi solder balls upon thermal cycling on board (TCoB). We quantitatively segment fatigue cracks and flux pores from 3D X-ray tomography data utilising a multi-level ML-workflow incorporating a 3D U-Net model. The data reveals that intergranular fatigue cracking is the predominant failure mechanism during TCoB and that dynamic recrystallisation precedes crack initiation. Moreover, we find that fatigue cracks are initiated at surface notches, flux pores and printed circuit board-metallisation intrusions. The work provides important insights regarding the underlying microstructural and mechanical mechanisms for recrystallisation and cracking, uniting the aspects of big-data analysis with ML-algorithms and in-depth understanding about the underlying materials science.

Electromigration of Power Devices Part 2: Power Device in Applications in Controlled Environment

In the power semiconductor industry, there is a continuous development toward a higher current capability of devices while device’s dimensions shrink. Although higher current is preferred, the reliability risk of the electromigration (EM) remains challenging. In the present study, a special EM test vehicle is used to investigate the pure EM behavior of power device, following our previous work. The selection of the test condition is discussed in detail, which is defined based on the temperature and current profiles of the device in the actual application, focusing on the applications of the power devices in a controlled environment, i.e., data centers or telecommunication servers. The current and temperature profiles of the device are discussed based on the device’s maximum power dissipation and its respective thermal design. The results show that the different combinations of currents and temperatures can lead to different ratios of acceleration factor between the temperature and the current. Consequently, an inappropriate selection of the testing condition can result in the over-domination of temperature over the current, leading to wrong conclusions. The effects of the PCB surface finish (both Ni and Sn plating) as well as different electron flow directions on the EM were studied. It is concluded that the maximum current that can be applied to a power device in the application within a controlled environment is rather limited by the cooling capability of the system than the EM induced device failure.

Analysis of competitive advantage factors in the power semiconductor industry

While the competitive advantage of Japanese companies in the semiconductor industry has declined significantly, the competitive advantage of Japanese companies in the power semiconductor field is still maintained. Based on the architectural theory that Japanese companies have strengths in industries that require matching, this study analyzed the factors of matching in the field of power semiconductors. As a result of comparing the relationship between the functional design, structural design and process design of logic ICs and power semiconductors, which are typical products of the semiconductor industry, there was a strong dependency between the functional design of power semiconductors and the process design. It was shown that the strong dependence between functional design and process design is one of the competitive advantage factors of Japanese companies in the field of power semiconductors.

Electromigration in Power Devices: A Combined Effect of Electromigration and Thermal Migration

Abstract In the power semiconductor industry, there is continuous development toward higher maximum current capability of devices while device dimensions shrink. This leads to an increase in current density which the devices have to handle, and raises the question if electromigration (EM) is a critical issue here. Generally, an EM failure can be described by the Black’s equation with temperature and current density as the main influencing factors. Normally, the current that the power packages need to handle lies in the range of 100 A. However, it should be noted that power devices exhibit asymmetric sizes of drain and source contacts. This may lead to higher current density at the source leads (area ratio drain/source: ~9× for PQFN 5 × 6). Nevertheless, the source lead area is still much larger than that of the flip chip bumps (i.e., 28 times larger than a 100-μm microbump). This typically enhances the safety of the power device with respect to EM. However, with regard to future development toward higher maximum current capability, we intended to investigate further on the EM of power devices. In the present work, we focused on the PQFN 5 × 6 package to study the EM behavior of a power device soldered on a printed circuit board (PCB). We employed the highest current (120 A) and temperature (150°C) that the stress test system could handle to study EM in accelerated mode. First fails occurred after ~1,200 h, which was much earlier than expected from previous flip-chip investigations. In addition, we found separation gaps in the solder joint between drain contact and PCB, which experienced the lowest current density in the whole test. Contradictorily, we observed only minor solder degradation at the source interface, regardless of the higher current density there. Nevertheless, the separating metal interfaces still correlated well with the current direction. Thermal simulations revealed that due to the self-heating of the device by the high current applied, both the drain and source leads were exposed to much higher temperatures (Tmax = 168°C) than the PCB board which was kept under temperature control at 150°C. This temperature difference resulted in a thermal gradient between the device and PCB, which, in turn, triggered thermal migration (TM) in addition to EM. As TM for the drain contact occurred in the same direction as EM, it enhanced the degradation effect and therefore led to a shorter time-to-failure at the drain. In contrast to this, such an enhanced effect did not occur at the source side. As a result, we observed higher solder degradation at the drain side, which we did confirm by switching the current direction in the test. To minimize the TM effect, a special EM test vehicle, which used a Cu plate instead of the metal-oxide-semiconductor field-effect transistor chip, was designed and fabricated. Thermal simulation verified that the device operated at similar temperatures as the PCB board. Using this setup, it was possible to study EM in an accelerated mode and, thus, investigate the pure EM behavior of the power device.

High-Voltage Temperature Humidity Bias Test (HV-THB): Overview of Current Test Methodologies and Reliability Performances

The high voltage temperature humidity bias test (HV-THB) has become increasingly popular for evaluating the performances of power semiconductor devices. Given the new challenges of the power semiconductor industry, several applications and devices need to be designed to withstand harsh environments during working operations, with a remarkable focus on high-humidity conditions. The HV-THB test allows one to activate and study different failure mechanisms which were not highlighted by the standard low voltage THB test, enabling new designs in several energy conversion fields, such as energy harvesting, industry and automotive applications. After a brief introduction of current test standards, this work goes through the current methodologies and state-of-the-art of the HV-THB test. The following sections are then dedicated to the knowledge about the failure mechanisms and the models for accelerated testing. Eventually, there is a section devoted to the main passivation materials in order to understand their effects on the HV-THB capabilities of the devices.

Electromigration in Power Devices

Abstract In the power semiconductor industry, there is continuous development towards higher maximum current capability of devices while device dimensions shrink. This leads to an increase in current density which the devices have to handle, and raises the question if electromigration (EM) is a critical issue here. Generally, an EM failure can be described by the Black’s equation with temperature and current density as the main influencing factors. Normally, the current that the power packages need to handle lies in the range of 100 A. However, it should be noted that power devices exhibit asymmetric sizes of drain and source contacts. This may lead to higher current density at the source leads (area ratio drain/source: ~8x for QFN 5×6). Nevertheless, the source lead area is still much larger than that of the flip chip bumps (i.e., 28 times larger compared to a 100 μm micro-bump). This typically enhances the safety of the power device with respect to EM. However, with regard to future development towards higher maximum current capability, we intended to investigate further on the EM of power devices. In the present work, we focused on the PQFN 5×6 package to study the EM behavior of a power device soldered on a Printed Circuit Board (PCB). We employed the highest current (120 A) and temperature (150 °C) that the stress test system could handle to study EM in accelerated mode. First fails occurred after ~1200 h, which was much earlier than expected from previous flip-chip investigations. In addition, we found separation gaps in the solder joint between drain contact and PCB, which experienced the lowest current density in the whole test. Contradictorily, we observed only minor solder degradation at the source interface, regardless of the higher current density there. Nevertheless, the separating metal interfaces still correlated well with the current direction. Thermal simulations revealed that due to the self-heating of the device by the high current applied, both the drain and source leads were exposed to much higher temperatures (Tmax = 168 °C) than the PCB board which was kept under temperature control at 150 °C. This temperature difference resulted in a thermal gradient between the device and PCB which, in turn, triggered thermal migration (TM) in addition to EM. As TM for the drain contact occurred in the same direction as EM, it enhanced the degradation effect and therefore led to a shorter time-to-failure at the drain. In contrast to this, such an enhanced effect did not occur at the source side. As a result, we observed higher solder degradation at the drain side, which we did confirm by switching the current direction in the test. To minimize the TM effect, a special EM test vehicle, which used a Cu plate instead of the MOSFET chip, was designed and fabricated. Thermal simulation verified that the device operated at similar temperatures as the PCB board. Using this setup, it was possible to study EM in an accelerated mode and, thus, investigate the pure EM behavior of the power device.

Optimization of Doping Profiles in Insulated-Gate Bipolar-Transistors Using a Large Scale Optimization Technique

There is much interest on the numerical and practical optimization of the doping profiles in semiconductor devices. This interest is mostly driven by the power semiconductor industry, which is in continuous search for higher breakdown voltage semiconductor switches that have lower on-state resistance, and high current handling capacity and switching speeds. Among the existing power semiconductor devices, insulated-gate bipolar-transistors (IGBTs) are becoming more and more attractive because of their high blocking voltage capabilities and on-state current. Although these devices suffer from a relatively lower switching speed compared to current state-of-the-art metal-oxide-semiconductor field-effect-transistors, IGBTs have already become the preferred switching devices in many power applications, such as induction heating applications, traction motors, etc. [1]. In this work we present numerical finite element optimization results for a realistic 70 mm-wide punch-through IGBT structure. The optimization focusses on the two-dimensional doping distribution of the gate, emitter and collector junctions, and of the drift and buffer layers in order to increase the breakdown voltage of the IGBT. The optimization method is based on an adjoint space technique that our group has recently developed for the design of nanoscale semiconductor devices, and which is adjusted here to compute the doping sensitivity functions of the breakdown voltage and on-state resistance in IGBTs [2-4]. These doping sensitivity functions show how sensitive the breakdown voltage and on-state resistance are when we add one additional acceptor or donor impurity at a particular location inside the semiconductor. Since the doping sensitivity functions provide information about the gradient of the breakdown voltage and on-state resistance with respect to the doping concentration they are instrumental for the numerical and practical optimization of IGBTs. As we will show at the conference, we are able to increase the breakdown voltage from approximately 300 V to over 700 V without deteriorating the on-state resistance of the transistor. In the full presentation we will describe how the adjoint method can be used to calculate the doping sensitivity functions of the breakdown voltage, on-state current and voltage, and on-state resistance. We will also present details about the numerical implementation of the optimization method, which is based on a modified gradient optimization appropriate for semiconductor devices. Note that most traditional optimization approaches such as the steepest descends method, the Broyden–Fletcher–Goldfarb–Shanno algorithm, or similar algorithms fail because of the doping concentration varies over many orders of magnitude, which vary can from region to region inside the same device.

Adjoint Method for Increasing the Breakdown Voltage and Reducing the On-State Resistance in Wide Band Gap Power Transistors

A central problem in the power semiconductor industry is the design of wide band gap (WBG) devices with high breakdown voltage (BV) and low on-state resistance (RON). This problem is particularly difficult to solve because high BV requires large devices, in which the separation between the source and drain electrodes in the case of FETs or anode and cathode in the case of p-n junctions is relatively large, while low RON requires relatively small devices with high doping concentrations. For any given semiconductor material there is a trade-off between BV and RON, trade-off that is generally given by the overall dimensions and geometry of the device. In this work we focus on the optimization of standard WBG MOSFET configurations [1], in which we optimize the doping profiles in order to increase the BV while keeping the on-state resistance constant. Our approach is based on applying an adjoint space technique that our group has recently developed for the design of nanoscale semiconductor devices, and which can be used to perform a multidimensional optimization of the doping concentration at each location inside the device using a doping sensitivity approach [2-4]. Note that traditional optimization techniques based on heuristic methods such as genetic algorithms or evolutionary methods are impractical in this case because of the large number of independent variables. For instance, for a finite element mesh with 104 nodes there are 104 independent variables (given by the doping concentration at each finite element), which makes the problem difficult to solve even on parallel or distributed computer clusters. The method that we introduce in this presentation is based on the computation of the doping sensitivity functions of the BV and RON, which show how sensitive the BV and RON are when we add one additional acceptor or donor impurity inside the semiconductor. The doping sensitivity functions are instrumental in the optimization of WBG power devices. As we will describe in the full paper, the doping sensitivity functions can be computed efficiently by using the adjoint method. They can be coupled with gradient-based optimization methods to compute the optimum doping profiles for acceptors, Na(r), and donors, Nd(r). At the conference we will describe the numerical implementation of the adjoint method for the optimization of WBG power devices and present sample simulation results for a few standard structures. Our initial results show that by properly designing the doping profiles in standard power transistors we can increase the BV by 15-20% without affecting the on-state resistance.

Reliability design of direct liquid cooled power semiconductor module for hybrid and electric vehicles

With the global interests and efforts in popularizing low carbon vehicles, automotive power module has been becoming one of the fastest growing sectors in power semiconductor industry. As working in a harsh environment, the performance and reliability requirements of automotive module are stringent than industrial products. In this work, an integrated direct liquid cooled power module with enhanced reliability for hybrid and electric vehicles (HEV/EV) is developed. The design and assembly of the module were optimized in terms of performance, weight, cost and reliability. The module is integrated Al direct liquid cooling structure, leading to about 40% reduction of weight and cost and almost 50% reduction of junction to heat sink thermal resistance. Therefore, the junction temperature stays below the upper limit at the worst operation case which enhances the thermal reliability and lifetime. By incorporating advanced die lead bonding, the parasitics can be reduced by 50%, which is beneficial to efficiency and reliability. Furthermore, the die and terminal attach technologies are investigated to improve reliability. The lifetime prediction under a typical driving cycle shows that the proposed module is capable of working in the whole vehicle service period.

3D TCAD Simulations for More Efficient SiC Power Devices Design

SiC devices become more and more prominent in the power semiconductor industry. Thanks to a technology that seems to be mature enough, SiC devices become more and more sophisticated. Therefore, they can be serious competitors to existing silicon devices in not so distant future at least for high temperature and high power applications. In addition to undoubtedly better electrical and thermal properties, SiC devices still require attention regarding their design. Indeed, the material is still more expensive than silicon and some limitations such as the inability to create deep p-n junctions prevent from re-using existing silicon design. Therefore, SiC devices should be designed so that the best trade-off between active area and breakdown voltage is achieved. In such a context, 3D TCAD can be become an interesting approach mostly thanks to modern computer farms.

Innovation in Power Semiconductor Industry: Past and Future

Power microelectronics plays an important role in many of the consumer and industrial applications today. With increase in demand for energy savings and efficient systems, the requirements for rapid advancement in MOS controlled power semiconductor device concepts and technologies are becoming more crucial than ever before. This puts a considerable pressure on industries to be innovative and competitive at the device, technology, manufacturing, and marketing levels. Today manufacturing companies are faced with intensifying competition and a turbulent economic environment. To some extent technology is seen as a means by which firms can strive to adapt to the requirements of this difficult and uncertain environment. On the other hand, rapid rates of change and associated shorter product cycles are themselves part of the difficulty, as is the increased blurring of long-established industrial boundaries (Kodama's, 1985) process of technological fusion. The growing complexity and increased pace of industrial change especially in power microelectronics are forcing firms to forge new alliances and to seek greater flexibility and efficiency in responding to market changes. The aim of this paper is to explore these aspects.

An Investigation of Lead Free and Bromine Free Technologies for Medium Power Semiconductor Packaging

ABSTRACTOver recent years there has been a growing interest in the removal or substitution of Lead, Bromine and other hazardous chemicals from electronic and electrical equipment. This relates primarily to products whose end of life disposal relies on the use of landfill sites or increasingly on recycling. The driving force for these changes come from both legislation such as that proposed by the European Union [1] and also from consumer awareness. The implications of the move towards more environmentally friendly electronics extend right down the level of discrete component packages including those produced in large numbers by the power semiconductor industry. In the present paper the technical challenges associated with the development of a lead and bromine free medium power packaging are discussed and the results of ongoing investigations are presented. The major challenges in this area relate not only to the substitution of key elements but also to ensuring compatibility with the higher reflow temperatures which may be associated with Pb-free surface mount processing. This raises particular issues with respect to the die attach material, which is often a high Pb soft solder; the encapsulation compounds which tend to rely on Bromine and Antimony compounds for their flame retardant properties; and the device plating which must be compatible with Pb-free board attach solders.

Applications of ESCA to fabrication problems in the semiconductor industry

Surface chemical states of materials involved in the fabrication of semiconductor devices can often alter device properties and performances, reducing product yield. X-ray Electron Spectroscopy has been applied to some problems of relevance in the power semiconductor industry. It was found to provide important information in areas like those of failure analysis, process improvement and technological development as well as basic research.

Open‐Tube Diffusion

In the power semiconductor industry, aluminum, the fastest diffusion p‐type species in silicon, has been used for years but due to the active nature of the process, it was only performed in closed‐tube systems. Now, however, aluminum diffusion has been achieved in an open ambient. The related properties of this diffusion technique, together with the characteristics of the devices made with this diffusion process, are described.